Carbon nano-tube field-effect transistors (CNFET) have emerged as a potential alternative field-effect technology to conventional deep-submicron silicon transistors. While operating under physical principles similar to complementary metal-oxide semiconductor (CMOS) silicon field-effect transistors, these devices offer several possible advantages in circuits including reduced short-channel effects, potential molecular-level control to reduce variability, and a hybrid three-dimensional integration in which active devices (CMOS on the bottom and CNFET on the top) will sandwich the metal interconnect layers. For any of these potential advantages to be realized, these devices must coexist with silicon CMOS FETs and must be able to leverage the existing investment in CMOS process technology. By combining CMOS-compatible CNFET fabrication with comprehensive circuit-focused device characterization, the PIs seek to further explore the potential advantage of CNFETs for real microelectronics applications while pursuing the development of viable circuits that combine CNFET transistors with conventional deep submicron CMOS technology.
