PI Name: Nazhandali Nazhandali,Leyla Institution: Virginia Polytechnic Institute and State University

With more than 98% of all programmable processors running in embedded mode that are expected to deliver increasingly more sophisticated functionalities, the ``power struggle" has become an increasingly critical issue. Power restrictions imposed by the so-called power envelope, further aggravated by the battery life in embedded systems, compel designers to trade performance for reduced power. Furthermore, hackers, unable to break the cryptosystems using theoretical methods, have turned to secret-revealing physical properties of these systems, such as varying power consumption, to deduce secret information; these attacks are known as power side-channel attacks. The objective of this proposal is to overcome these two closely related challenges resulting from high levels of power consumption and from high degrees of variations in power levels that reveal secret information. The proposal's uniform approach to solve various facets of these problems is the exploitation of the subthreshold-voltage technology. This technique is an extreme case of voltage scaling so that the operating voltage is below the ?threshold? that turns the transistors on. This proposal plans to advance the state of secure and low-power embedded system design through innovations in subthreshold-voltage microarchitectural techniques focusing on two specific research thrusts: 1) designing a multi-core architecture with subthreshold voltage cores, which is expected to deliver the same performance as a regular design while consuming 90% less power, and 2) partitioning a secure design into security-critical and non-critical regions so that the former runs at subthreshold voltage and the latter in superthreshold, thus maximizing the performance and minimizing the risk of side-channel attacks.

This proposal aims to facilitate the use of subthreshold-based hardware design for embedded system designers by developing CAD tools, architectural techniques, and performance/power profiling-based case studies. This, in turn, will result in increased use of this technology, enabling the achievement of new low-power milestones hitherto impossible because of the barriers imposed by traditional technologies. Some of the foreseeable application areas that could be significantly improved by advancing the targeted thrusts include electronic passports, wireless security cameras, rescue and recovery robots, and handheld landmine detectors. As part of the educational aspect of this proposal, a hands-on pre-college program, called ?Embedded for Life,? will be established in order to present the creative and beneficial aspects of the computer engineering discipline. It will showcase the use of embedded microprocessors in bettering our lives. This program, which will be developed and publicized in collaboration with IEEE, SWE, and NSBE, will encourage participation of women and minorities in computer engineering on a local and national level.

Project Report

Power restrictions imposed by the so-called power envelope, further aggravated by the battery life in embedded systems, compel designers to trade performance for reduced power. Furthermore, hackers, unable to break the cryptosystems using theoretical methods, have turned to secret-revealing physical properties of these systems, such as varying power consumption, to deduce secret information; these attacks are known as power side-channel attacks. The objective of this project was to overcome these two challenges resulting from high levels of power consumption and from high degrees of variations in power levels that reveal secret information. The project's uniform approach to solve various facets of these problems was the exploitation of the near/subthreshold-voltage technology. In a broader framework, the project helped facilitate the use of near/subthreshold-based hardware design for embedded system designers by developing CAD tools, architectural techniques, and performance/power profiling-based case studies. The contributions of this project are presented under four topics. Fast approximation framework for timing and power analysis of ultra-low-voltage circuits Ultra-low-voltage operation can greatly reduce the power consumption of circuits. However, there is no fast, effective, and comprehensive technique for designers to estimate power, delay, or effects of process variation of a design operating in the ultra-low-voltage region. We have developed a simulation framework that can quickly and accurately characterize a circuit from nominal voltage to the sub-threshold region. The framework uses the nominal frequency and power of a target circuit, obtained using gate-level or transistor-level simulation tools, and normalized ring oscillator curves to predict delay and power characteristics at lower operating voltages. Specific contributions include a weighted average method, as well as a methodology to estimate the effects of process variation. The weighted averages framework takes into account the types of gates that are used in the circuit and critical path to give a more accurate power and timing characterization. Despite being several orders of magnitude faster than other approximation techniques, the errors are less than 20%, which is consistently less than other methods. Power side-channel resistance using subthreshold operation We have shown that Sense Amplifier Pass Transistor Logic (SAPTL), which is typically operated at near/subthreshold region, is a promising choice for increasing power side channel attack resistance while maintaining energy efficiency. Furthermore, we have presented an automatic approach to generate big SAPTL logic blocks (e.g. SBOX) from a synthesized verilog code. We have mounted differential power analysis attacks on the designed circuits and calculated the success rate over different noise conditions. Our results show that SAPTL consumes comparable amount of energy with respect to static CMOS while significantly improving resistance to power side channel attacks. Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture We have developed a parallel implementation of a 1024-point FFT operating with a subthreshold supply voltage. Our hybrid FFT design partitions a sequential butterfly FFT architecture into two regions, namely memory banks and processing elements, such that the former runs in the superthreshold region and the latter in the subthreshold region. For a given throughput, the number of parallel processing units and their supply voltage is determined such that the overall power consumption of the design is minimized. For a 1024-point FFT operation, our parallel design is able to deliver the same throughput as a serial design, while consuming 70% less power. Design of Energy-Efficient, Adaptable Throughput Systems at Near/Sub-threshold Voltage We have leveraged the benefits of voltage scaling methodology for obtaining energy efficiency and compensated for the loss in throughput by exploiting parallelism present in the various DSP designs. We have shown that such a hybrid method consumes 8%-77% less power, compared to simple dynamic voltage scaling over different throughputs. We have studied such system architectures in two different workload environments: static and dynamic. We have shown that to achieve the highest level of energy efficiency, the number of cores and the operating voltages vary widely between a BASE design, where effects of process variation is ignored, versus a Process Variation-Aware (PVA) design. We have demonstrated that the PVA design enjoys an average of 26.9% and 51.1% reduction in energy consumption for the static and dynamic designs, respectively. To prove our concept, we fabricated a prototype chip in 90nm IBM technology. The chip consists of 8 homogeneous FIR cores, which are capable of running from near-threshold to nominal voltages. In our 20 chip population, we observed 7% variation in speed among the cores at nominal voltage (0.9V) and 26% at near threshold voltage (0.55V). We also observed 54% variation in power consumption of the cores. We have shown judicious selection of cores and their operating voltage in our chip can result in 6.3% to 28.2% reduction in power consumption for high- to low-throughput workloads.

Agency
National Science Foundation (NSF)
Institute
Division of Computer and Communication Foundations (CCF)
Application #
0747262
Program Officer
Sankar Basu
Project Start
Project End
Budget Start
2008-08-01
Budget End
2014-07-31
Support Year
Fiscal Year
2007
Total Cost
$412,077
Indirect Cost
City
Blacksburg
State
VA
Country
United States
Zip Code
24061