The successive innovations in semiconductor manufacturing over the last 35 years of Moore's law have turned what used to be a room-sized computer system into a single chip composed of billions of transistors. These levels of integration have forced a change toward parallelism in computer system design, including both single-chip multiprocessors and systems-on-a-chip. Today, these chips have a few tens of individual processors but future scaling will make hundreds or thousands available on a chip. Critical to the success of such systems is the hardware network that enables the processors on the chip to communicate with one another. Today's chips typically employ simple networks-on-chip (NOCs) such as bus, ring, or small grid. Future systems with numerous processors will need scalable and innovative NOCs to provide high communication bandwidth, low latency, and low power consumption.
This project seeks to develop scalable NOCs that are well suited to switch and wire capabilities in emerging chip fabrication technologies. In particular, the project would investigate new NOC topologies that exploit the enormous number of on-chip wires while reducing the number of hops to travel from a source to a destination. A second challenge is avoiding congestion in the network, much like avoiding automobile traffic congestion at rush hour. The investigation will develop new methods of monitoring the status of the routers and links in the network so that network messages can route themselves around network hotspots, improving network latency and bandwidth for all traffic. An important outcome of this research would be a public repository of network traces for different types of on-chip network traffic that will help improve the experimental methods of all NOC researchers.
