The focus of this project is the development of an integrated methodology for managing noise that addresses the multiple interactions among different noise sources to support the design of next generation multi-core mixed-signal systems-on-chips (SoCs). Accurate, yet computationally efficient noise models will be developed and combined with noise reduction techniques to effectively control the signal characteristics within a system. Leveraging the classical noise propagation model from communications, a novel unified approach will be applied to model noise generation, propagation, and reception among diverse system components, supporting the development of aggregate noise cancellation techniques. Design tradeoffs to alleviate the effects of multiple noise sources will be investigated and design guidelines will be developed. The interdependence among diverse noise effects at the device, circuit, and multi-core levels will be investigated and design strategies that minimize noise across mixed-signal components will be developed. Emphasis will be placed on the global features responsible for generating and propagating noise among different system components, such as the power distribution networks, the global interconnect lines, the inter-core synchronization schemes, and the silicon substrate. The sensitivity of the noise models and reduction techniques to process and environmental variations will also be investigated. The ultimate objective is that upon completion of this project, signal uncertainty in analog circuits and delay uncertainty in digital circuits due to multiple noise effects in multi-core SoCs will be better understood and accurately modeled in a computationally efficient manner, while integrated noise reduction methodologies will be developed to design the next generation of high complexity, high performance integrated circuits.
These research results will provide new directions for educational initiatives targeting both university teaching and research activities in the broader academic community. Undergraduate projects demonstrating the practical aspects of the research results will be devised in collaboration with graduate students. A course related to the research will be developed and offered to graduate and senior undergraduate students with disparate backgrounds. A tutorial will be prepared for presentation at major conferences. The PI will also participate in a University program intended to enhance minority enrollment in graduate engineering and science programs. The intellectual and social objectives of this project are intended to greatly surpass existing limitations in the system-on-chip design process, enabling the development of future generations of multi-core, mixed-signal SoCs, while contributing towards the advancement and diversity of the science and engineering workforce.
Outcomes With increasing integration densities, noise has become a primary bottleneck in next generation multi-core SoC systems. Due to decreasing physical dimensions of the device and interconnect and increasing integration levels, noise coupling has a significant effect on circuit performance. Noise greatly affects signal delay uncertainty, power dissipation, and synchronization; therefore, the primary focus of this project has been to develop effective noise analysis and mitigation techniques and methodologies, thereby enhancing the overall performance of an integrated circuit. During the term of this grant, multiple noise analysis, design, and optimization aspects were investigated. The research results can be separated into eleven categories: 1) developed an optimization procedure for combined shield and repeater insertion, while considering multiple constraints; 2) reduced signal delay uncertainty within the combinational logic chain; 3) developed a design methodology for interconnect shielding under the presence of power/ground noise; 4) analyzed and optimized interdigitated power and ground distribution networks for both a single and multi-layer structure; 5) developed a technique for efficiently estimating IR drops within mesh structured power distribution networks; 6) analyzed substrate isolation techniques based on a closed-from model to estimate noise propagation within the substrate; 7) designed an ultra small point-of-load voltage regulator; 8) estimated the worst case noise within power/ground networks; 9) developed co-design strategies for placing multiple on-chip decoupling capacitors and power supplies; 10) developed a link breaking methodology, reducing noise within mesh structured power networks; and 11) estimated noise for TSV-based 3-D integrated systems. Four graduate students contributed to the development of these design, analysis, and circuit optimization techniques and methodologies. Three of these four students have completed their requirements for the Ph.D. degree and the other student will soon graduate. Their thesis topics are closely related to the project topic of managing noise in next generation systems-on-chip. During the duration of this project, five books, three book chapters, two Ph.D. dissertations, 24 journal publications, 36 conference papers, and seven workshop presentations have been published or are currently under review. The students involved in this research projects gained important insight into understanding the noise characteristics of nanoscale integrated circuits. These methodologies have been transferred to US industrial companies to support further development of next generation integrated circuits. The design and analysis flows have been integrated into existing company design flows, supporting enhanced noise analysis and design optimization capabilities. Graduate Students Involved with this Project Emre Salman graduated with his Ph.D. degree in April 2009 and was partially funded by this NSF grant. His dissertation is titled "Switching Noise and Timing Characteristics in Nanoscale Integrated Circuits." He is currently an Assistant Professor with the Department of Electrical and Computer Engineering at the State University of New York at Stony Brook. Renatas Jakushokas graduated with his Ph.D. in July 2011 and was partially funded by this grant. His dissertation is titled "Physical Resource Allocation for On-Chip Power Delivery Systems." He currently works as a Senior Engineer at Qualcomm Corporation in San Diego, California. Selcuk Kose graduated with his Ph.D. in June 2012 and was partially funded by this grant. His dissertation is titled "High Performance Power Delivery for Nanoscale Integrated Circuits." He is currently an Assistant Professor with the Department of Electrical Engineering at the University of South Florida in Tampa, Florida. Ioannis Savidis is currently working towards his Ph.D degree and was partially funded by this grant. His research interests include design, modeling, and analysis methodologies for high performance 3-D integrated circuits, with an emphasis on electrical modeling and characterization of TSVs, signal and power integrity, and power and clock delivery for 3-D stacking technologies.
