Microscopic manufacturing flaws, such as the localized narrowing of interconnection lines, via voids, and pin holes in insulating gate oxide, are a major reliability concern in nanometer digital integrated circuit technologies. Such defects are difficult to detect during production testing because they often do not cause catastrophic malfunction in the circuit; instead, circuit switching delays may be marginally increased along the signal paths containing the defect. Since a complex chip contains billions of circuit paths of varying lengths, and circuit clock timing is designed to accommodate the longest path delay, small delay defects on short paths can remain hidden within circuit timing slacks during post manufacturing testing. However, such defects can often cause errors under worse case operating conditions or degrade further under the stress of field operation to cause early life reliability failure. These small delay defects can potentially be detected through more aggressive timing tests, using faster than rated clock frequencies, to capture and expose any erroneous response due to the excessive delays along short paths. This requires the use of the scan design-for-test methodology which provides full access to the internal flip-flops in sequential designs, and can thereby allow circuit timing to be observed for single cycle operation. Scan delay tests check if signal propagation delays along the targeted paths in the circuit, activated by two vector delay test patterns, fall within the applied ?launch? to ?capture? clock period. However, because single cycle scan tests operate the circuit in a manner which is different from normal multi-cycle sequential operation, there is increasing evidence that the observed circuit timing may not reflect true circuit delays in normal continuous functional operation. Factors such as power supply noise, coupling and cross talk from abnormal switching activity, variations in die thermal profile, and ?clock stretching? can all significantly impact scan test timing. Normal manufacturing process variations further add to these test timing uncertainties, making the detection of small delay defects extremely challenging. This research takes the view that it may be impractical to observe true circuit functional timing with sufficient accuracy using a surrogate scan based timing test to reliably detect small delay defects. Instead, such defects are better detected by identifying abnormal switching delays (timing anomalies) through a comparison of timing test results from a matched population of parts. Here the scan tests are not used to test circuit timing against a fixed rated clock (e.g. as required for speed binning), but only to identify anomalous parts that display abnormal delays relative to the statistical norm for the population. Critically, this relative rather than absolute timing evaluation eliminates the need for the scan timing tests to accurately match functional timing. The impact of common mode factors such as power supply and coupling noise, clock stretching, etc. is factored out by the comparison test. Non-functional test inputs can also be used by the test, with multiple fast clocks, to achieve high coverage of small delay defects, even on short paths. Preliminary research has experimentally shown that if test responses from adjacent die are compared, delay defects of size less than 5% of the critical path can be reliably detected. This research is developing and evaluating a number of new methodologies to make such silicon ?calibrated? scan delay testing practical and commercially attractive. The new delay test methodologies will be evaluated using specially designed test chips. A longer term goal of the proposed research is to carry out experimental studies, in partnership with industry, to validate the methodologies developed on volume production parts.
This research project will help improve the research capabilities of Alabama, an EPSCoR state. Results from the research will also be incorporated in advanced courses taught by the PI, both at Auburn and off campus, through the IEEE Test Technology Education Program. The PI works closely with the Historically Black Tuskegee University located near Auburn, including cooperating on an ongoing joint NSF Computing Research Infrastructure (CRI) grant in the VLSI testing area. Tuskegee students take graduate courses at Auburn University, and some are jointly advised by Auburn faculty. Tuskegee Ph.D. students, who have taken graduate courses with the PI, will be encouraged to participate in this research. This will further strengthen the research interaction between Auburn and Tuskegee, which is helping to attract minority U.S. citizens to graduate studies the computing field.
