As more compute, memory, and storage resources continue to be integrated within multicore chips and multiprocessor systems built from multicores, significant advancements in the interconnect architecture that enable efficient connectivity and sharing among multiple heterogeneous system resources (including caches) across multiple hierarchy levels are needed. Escalating energy and reliability problems with nanometer technology scaling are making over-provisioning and static allocation of resources less viable for meeting increasing performance demands. This exploratory research investigates new and innovative on-chip network designs and network-driven shared resource management techniques that have the broader impact of laying important groundwork for realizing adaptive, fault-resilient, low-cost, energy- and performance-efficient multicore parallel computing systems with hundreds to thousnads of nodes.

Project Report

This project investigates new and innovative communication architectures and resource management techniques that better enable the realization of adaptive, power-aware, performance-efficient, fault-resilient, and low-cost multicore parallel processing systems. The goals of this research are to investigate new methodologies and techniques for integrating the design and efficient management of interconnection network, processor, and memory subsystem resources holistically to deliver more globally-optimal solutions. Through a holistic approach for network-driven shared resource design and management in multicore-based systems, this exploratory research has laid important groundwork for significant breakthroughs in this challenging problem area. System interconnect designs have been proposed that optimize performance, energy, and system resiliency by exploiting expected communication behavior of application workloads at and across multiple layers of the system architecture through efficient mapping onto domain-specific and/or reconfigurable interconnect resources (i.e., network interfaces, links and routers) composing hybrid topologies implementable in advanced technologies. Intellectual merits of the project include contributions along the following research lines: a holistic design approach for exploring on-chip networks and communication architectures; efficient on-chip network bandwidth provisioning techniques that support quality-of-service requirements while minimizing chip resources and power consumption; proactive and reactive network resource management techniques for dynamic allocation and reconfiguration to enable energy efficiency across multiple system interconnect layers; effective shared cache/memory management techniques that reduce latency and improve resource utilization; and light-weight, in-network hardware for monitoring memory access patterns and dynamically provisioning network resources. The research contributions of this project advance fundamental understanding of the interplay between communication behavior of parallel applications and the design of multicore communication architecture, inclusive of on-chip interconnection network and cache/memory design, thus laying the groundwork leading to more scalable and efficient on-chip resource design and management solutions. Outcomes of the research are published in international conference and journal venues to impact more broadly the field of computer systems architecture.

Project Start
Project End
Budget Start
2009-09-01
Budget End
2013-08-31
Support Year
Fiscal Year
2009
Total Cost
$261,244
Indirect Cost
Name
University of Southern California
Department
Type
DUNS #
City
Los Angeles
State
CA
Country
United States
Zip Code
90089