Ensuring reliable computation at the nanoscale requires mechanisms to detect errors. The PIs propose fundamental research for developing efficient hardware techniques to support online error detection and manufacturing test by monitoring invariant relationships. These invariant relationships naturally occur across multiple levels of digital logic and across multiple time cycles. Violations of these relationships indicate that errors have occurred, either because of transient faults or manufacturing defects; thus monitoring them in hardware can significantly improve circuit reliability. While other techniques exist for error detection, this approach has several advantages, including significantly lower power dissipation, no high-level information requirements, fine-grained optimization capabilities, and providing a potentially powerful source of diagnostic information. A key challenge in this project is the efficient selection of an optimal set of implications to include in the hardware, such that desired reliability is obtained with low overhead.
Reliable operation of logic devices is key for the continued push for smaller and faster electronic circuits. Any benefit in performance and power brought forth by rapid scaling of transistors cannot be fully realized if high reliability cannot be guaranteed for systems composed of these devices. The proposed research is a collaborative effort between Brown and Bucknell Universities. The project involves undergraduate students, many of whom are women and under-represented minorities. The PIs will use this project to create new opportunities to expose undergraduates to research, and to develop outreach workshops to encourage women and under-represented minorities to pursue degrees in computing.