Modern computer chips contain billions of tiny transistors connected by wires. The massively integrated circuits (ICs) are prone to wear out and degradation during their lifetimes. When electric current flows in a microscopic wire, the moving electrons collide into diffusing metal atoms and cause a gradual ion movement. This current-flow-induced material transport is called electromigration (EM). The electromigration phenomenon is a major source of interconnect degradation. Over time EM may cause wire breaks or shorts leading to circuit malfunction. Greater current densities, wire geometry or material imperfections, and increased temperature worsen EM. In the past, improvements in interconnect manufacturing kept pace with interconnect scaling and allowed for relatively simple ways of keeping EM at bay by capping current densities. Interconnect scaling is now approaching the point where the existing models and assumptions are no longer valid. At the same time chip?s thermal conductivity decreases while the density of currents carried by the on-chip wires and the operating power steadily increase causing significant self-heating. These effects bring again EM to the forefront and cause that it now poses a serious reliability threat for working chips. There is an urgent need to develop a comprehensive chip-level EM analysis tool. The PI proposes to develop a physical EM simulator to understand failure mechanisms in various interconnect configurations. The PI will use the simulator to develop metrics for wire time-to-failure estimates. The PI proposes to develop statistical models of interconnect failure and a chip-level analyzer of electromigration degradation effects. Interconnects whose expected lifetimes are shorter than desired can be modified. The will develop such modification strategies as well.

This work supports the US semiconductor industry by addressing a vital research problem that may affect the integrated circuits scaling trends. The proposed techniques would be useful for designers because the worst circuit degradation conditions occur in small regions of the chip that can be identified and resolved. In addition, the tools to be developed may also help process engineers to study the effects of new materials on circuit level properties. The proposed research activities will also serve as a platform for training PhD students who will be well prepared to work in modern industry or academia.

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University of California Santa Barbara
Santa Barbara
United States
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