Multi-core processors are becoming prevalent and provide means for continuing to increase our computational capacity. These emerging platforms with multiple processing cores on chip offer the capability to run multiple programs simultaneously, thereby increasing the processing power of computing systems. However, since the running programs often share multi-core resources, execution interference effects between such programs can hurt their performance. Often times, software obliviousness to this underlying hardware behavior exacerbate the multi-core performance problem. Such adverse effects limit our computational progress in areas where interference can be detrimental such as high-performance computing and cloud computing, and could further complicate the predictability and deployment of these advanced processors in mission-critical domains such as avionics and automobiles. Therefore, understanding software behavior and Interference effects on multi-core processors is crucial to harnessing their full potential.

In this research the investigators do preliminary studies of the issues arising from execution interference between multiple software threads on multi-core processor platforms. This research involves revisiting how hardware resource management can account for application-level constraints (such as performance isolation, fairness, and priority) by enhancing the interface between hardware and the Operating System (OS), and studying the hardware and software overheads. This research lays the groundwork for the hardware-OS interaction based on active fine-grained monitoring of resources and a two-way adaptation between both the hardware and OS to tightly control the effects of interference between threads.

Project Report

For decades now, the basic interaction between hardware and software has remained unchanged: the OS (operating systems) handles the execution of multiple applications, and assumes that smart compilers know how best to exploit hardware resources efficiently. It is often assumed that, as hardware capabilities increase -- with faster processors, and ever increasing numbers of computing cores -- applications will trivially take advantage of the turbo-charged hardware by merely choosing an application to execute (i.e. schedule it) and "getting out of the way". Unfortunately, such an approach on modern-day computing platforms like multi-core chips, results in performance artifacts and degradations as applications on different cores interfere with each other and contend for shared hardware resources. It is essential to effectively harness the potential resulting from increasing core counts and continue the progress that computers have enjoyed over the past several decades. This requires a closer collaboration between software and hardware than has traditionally been customary. In this project, the Principal Investigators (PIs) and their research groups have performed preliminary studies to better understand execution interference between multiple software computations running on multi-core processor platforms, and have produced research publications that aim to bridge the significant gap between software and hardware. First, the PIs have investigated the impact of how execution on different cores impacts the system's consumption of power. Experimental studies show that even after balancing performance on various cores, the power consumption by the respective cores could still vary. Such variations are a result of differences in application code executing on the chip, execution time artifacts resulting from minor variations in the underlying core microarchitecture and so on. This disparity in power consumption both drains batteries faster and affects the processor's heat density -- making it hard to leverage the multi-core processors in most computing environments including mobile platforms. This result has a significant influence on how a programmer writes and tests their programs; in addition to making sure that programs are functionally correct, they must keep track of an application's power consumption behavior. This project has highlighted the need for understanding power in multi-core applications and their interactions with the processor micro-architecture. Second, the PIs have researched a novel software architecture that is capable of much finer-grained interactions with hardware. A typical software system is composed of code with large numbers of different patterns and means for using the hardware. The PI's architecture decouples software with different "hardware finger-prints" into disparate components, and opens the possibility for a better matching of components with specific requirements, to hardware that best accommodates those needs. Components, though beneficial for isolating software with specific requirements, also raise challenges that the PIs address. For example, to break software systems into components requires effective and efficient means for them to communicate with each other, a focus of this work. By creating a novel software architecture based on components, the PIs have enabled the potential for a more effective mapping of specialized software to comparably specialized hardware to effectively bridge the gap between hardware and software. The PIs have also integrated this research with educational initiatives by engaging students at The George Washington University in this research, and by integrating the insights regarding delicate interplay between software and hardware into the GWU undergraduate and graduate courses on computer architecture and operating systems. Additionally, the PIs have mentored seniors in their capstone projects, efforts which have resulted in published research with significant contributions by the undergraduates. An outreach effort by the PIs has also yielded a number of lectures at a local high school exposing the students to the underlying technology that powers many of the services that they use, ranging from their cell phones to social media applications. These efforts have not only increased an understanding of the interactions between hardware and software, but have also risen awareness about the integration of technology into our lives.

Agency
National Science Foundation (NSF)
Institute
Division of Computer and Communication Foundations (CCF)
Type
Standard Grant (Standard)
Application #
1117243
Program Officer
Almadena Y. Chtchelkanova
Project Start
Project End
Budget Start
2011-09-01
Budget End
2013-08-31
Support Year
Fiscal Year
2011
Total Cost
$139,846
Indirect Cost
Name
George Washington University
Department
Type
DUNS #
City
Washington
State
DC
Country
United States
Zip Code
20052