To maximize performance, modern processors attempt to execute as many instructions as possible in parallel. This requires the use of branch predictors to guess which instructions will be executed next in an effort to keep the processor busy. However, the penalty associated with incorrectly guessed branch outcomes has a great impact on performance. Despite being studied extensively and improved steadily over the past two decades, branch prediction remains to be critical for achieving high performance and low power.

This project introduces a new direction in the design of branch predictors by providing insights into why branch predictors fail in predicting specific instances of dynamic branches. The research focuses on developing Complementary Branch Predictors (CBP), which can be added to any conventional branch predictor (BP). CBPs intelligently track the branches that are incorrectly predicted by a BP. A CBP complements the BP by providing corrective predictions for when and where a BP fails to predict the correct path. Given that modern BPs are already highly accurate, CBPs end up providing corrective predictions for the hardest-to-predict branches. Consequently, tightly-coupled BPs and CBPs form a new class of branch predictors that are fast, highly-accurate and power-efficient. This research explores the design space of this new class of branch predictors to achieve higher performance, lower power, and lower hardware budget.

The findings from this project have the potential to significantly change the design of future branch predictors. The PI will collaborate with industry partners to further increase the broader impact. The research will engage graduate and undergraduate students and promote the participation of underrepresented groups.

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University of Rhode Island
United States
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