One of the most critical challenges in todays nanoscale VLSI design is the lack of predictability in analysis and optimization. As VLSI technology continues scaling in the nanometer domain, VLSI systems are subject to increasingly significant parametric variations coming from not only the manufacturing process but also the system runtime environment. Increasingly significant parametric variations lead to increasingly significant variations in IC timing performance, power consumption, and other product metrics. Existing VLSI statistical analysis techniques cannot accurately and efficiently capture such variations; this greatly compromises design optimization and design convergence, affecting product quality and time-to market.

In this work the PIs plan to develop techniques for signal probability-based statistical timing analysis (SPSTA), which would achieve accurate performance estimates for different inputs, rather than input-oblivious pessimistic delay bounds. In this project, the PIs propose to build on the foundation of SPSTA to enable a new, predictive and less-pessimistic VLSI implementation methodology. Core techniques will span VLSI statistical analysis, delay test ATPG, and optimization techniques that exploit improved predictability. Specifically, there are three thrust areas in this project, and it is expected that that these techniques will outperform existing alternative techniques.

The outcome of this project is critical to the cost-effective continuation of semiconductor technology scaling (i.e., Moore's Law), and to maintaining growth of the semiconductor industry's economic engine in the coming years. The broader impacts of the proposed project can be further measured by a strong education program including curriculum development and research training which incorporate statistical VLSI analysis and optimization techniques into the computer engineering programs at the PIs? institutions, and into course infrastructure that is broadly and openly available to others online.

Following their established practices of well over a decade, the PIs will broadly disseminate their research results by publication, industry collaboration, and online posting of open-source software. This project will also allow the PIs to broaden participation of students from under-represented groups based on the minority institute status of UT San Antonio; it will help educational initiatives that are aimed at preparing the San Antonio regional economy to transform into a technology-oriented one.

Project Start
Project End
Budget Start
2011-09-01
Budget End
2014-08-31
Support Year
Fiscal Year
2011
Total Cost
$249,999
Indirect Cost
Name
University of California San Diego
Department
Type
DUNS #
City
La Jolla
State
CA
Country
United States
Zip Code
92093