The performance growth in uniprocessor (single core) performance resulting from improvements in semiconductor technology has recently slowed down significantly. Sequential applications or sequential portions of parallel applications require further advances to improve their performance. Today's processors complete instructions in their program order, which is a major performance bottleneck because any long-latency instruction, such as access to memory, delays completion of all subsequent instructions. This project aims to achieve higher single core performance by defining a new, compiler assisted mechanism for out of order instruction completion. It investigates how the use of compile-time program knowledge can be passed to the hardware and be used to simplify the architectural checks required for such out of order completion. The architecture of a standard processor is fully preserved and legacy software can execute without modification. The out-of-order instruction commit mechanism will use a novel compiler/architecture interface. The compiler provides information about instruction ``blocks'' and the processor uses the block information to decide which instructions can be committed out of order and when. Some blocks are guaranteed to be data independent blocks which allows instructions from different such blocks be committed simultaneously and out of order. Other blocks have data or control dependencies and require in-order execution and in-order commit. Micro-architectural support for the new commit mode is driven by the block information, which significantly simplifies the hardware. Exception handling is also simplified with compiler assistance. The new commit mechanism will effectively increase the size of the instruction window allowing more cache misses to be overlapped for both L1 and L2 caches. The project will also investigate additional compiler and architecture optimizations to further improve performance.