Micro-chips are at the heart of modern microelectronic systems for computing, communication, entertainment, and other consumer electronics. In order to design and manufacture the next generations of complex microelectronic systems, major innovations in the design of Electronic Design Automation (EDA) software are needed. This project focuses on developing novel EDA software. In the past 50 years, the exponential growth of the semiconductor industry has been primarily fueled by the continuous advancement in Integrated Circuit (IC) manufacturing technology, allowing the industry to produce chips with ever-increasing numbers and ever-decreasing sizes of transistors and wires. Today, the most advanced silicon chips have billions of transistors and tens of miles of wires, and the minimum feature size on a chip is less than 20nm. Lithography continues to be the backbone of chip manufacturing. In advanced IC technology, lithography has become the bottleneck for the chip design process. Design for Manufacturing (DFM) is no longer an option but a necessity. Since physical design determines the locations and geometries of all the transistors and wires, it must understand the down-stream lithography process so that the layout patterns generated are printable on silicon. This is a challenging problem and the requirements oftentimes are non-intuitive to the designers. In this proposal, we study lithography-aware physical design for several leading next-generation lithography (NGL) technologies. The NGL technologies considered here are triple-patterning lithography (TPL), self-aligned double patterning (SADP), directed self-assembly (DSA) and extreme ultraviolet (EUV) lithography. All the proposed topics are critical to their respective NGL technologies and their solutions are expected to greatly impact future generations of micro-chip design for years to come.

The proposed research will advance knowledge in Electronic Design Automation (EDA). It will also add new knowledge to other fields such as scientific computing and combinatorial optimization since ultimately we will need to solve large scale optimization problems. The broader impacts of this project include Very Large Scale Integration (VLSI) technology advancement and the education of next generation engineers. VLSI circuits are at the heart of modern information and communication systems. The proposed research improves the design and manufacturing of VLSI circuits, which will benefit society at large. New research results will be passed on to undergraduate and graduate students through dissertation research, course projects, homework, and classroom teaching.

Project Start
Project End
Budget Start
2013-08-01
Budget End
2017-07-31
Support Year
Fiscal Year
2013
Total Cost
$450,000
Indirect Cost
Name
University of Illinois Urbana-Champaign
Department
Type
DUNS #
City
Champaign
State
IL
Country
United States
Zip Code
61820