The end of Dennard Scaling, i.e., as transistors get smaller the power density is no longer constant, has led to a large number of inactive or significantly under-clocked transistors on modern chip multi-processors in order to comply with the power budget and prevent overheating. This so-called ?dark silicon? is one of the most critical constraints that will hinder scaling in accordance with Moore?s Law in the future. Additionally, off-chip memory bandwidth has also proven to be a major performance limiting factor, especially for multi- and many-core processors.

To address these concerns, this project proposes a novel design in which off-chip pins can dynamically switch between supplying power and transmitting signals. The circuit implementation for the proposed dynamic pin switching design, requiring only minor changes to existing processor and motherboard circuitry, will be investigated. Many issues including the impact of interfacing with the DRAM and the power delivery network, signal transmission and integrity, thermal issues, and area overhead will be thoroughly and carefully considered. A switchable pin design could be used to mitigate dark silicon by delivering extra power or to boost processor performance by increasing memory bandwidth. The broader impacts include incorporating the research advances into undergraduate and graduate education, as well as K-12 outreach activities.

Project Start
Project End
Budget Start
2014-08-01
Budget End
2017-07-31
Support Year
Fiscal Year
2014
Total Cost
$400,000
Indirect Cost
Name
Louisiana State University & Agricultural and Mechanical College
Department
Type
DUNS #
City
Baton Rouge
State
LA
Country
United States
Zip Code
70803