Transistor aging refers to the phenomenon that a transistor degrades with use over time. Hence, as digital chips are used, transistor aging reduces their performance and increases power consumption. Aging also causes some chips to fail prematurely during their expected lifetimes (called lifetime failures). Since such failures can corrupt user data, cause expensive system downtime, and require expensive maintenance, industry practice requires lifetime failure rates to be of the order of 10 to 100 parts per million. This project will develop completely new methods and CAD tools for design and testing of digital chips to combat aging in uniquely efficient ways. These new methods and tools will dramatically improve yield, dramatically reduce power, and provide chips with extremely low lifetime failure rates, even as aging continues to grow in severity as we approach the end of Moore's Law. In turn, the society at large will reap significant benefits of this research, since lower cost digital systems with low lifetime failure rates will help improve many essential services, especially health, security, and finance. In addition, this project will train students and industry experts in the art and science of aging and its mitigation and prepare them for the era near and beyond the end of Moore's Law. Also, significant outreach effort will ensure that undergraduate students and students from groups underrepresented in STEM will participate in this research.
This project has identified and will address three major limitations of existing aging research: serious inaccuracies of existing models in estimating long-term aging for real-life chip usage, the inability of existing memory designs to combat the most common type of memory aging, namely asymmetric aging, and the fact that existing approaches for post fabrication chip testing either provide extremely low yields or unacceptability high lifetime failure rates due to aging. Specifically, this project will develop completely new methods and tools for aging, demonstrate their effectiveness via extensive simulation studies and experiments on test chips, disseminate results and share new tools with academic and industry experts, and train students.
