The design of systolic arrays for implementing Affine Recurrence Equations is being carried out. The goals of this research are (a) the design of an automated system for generating systolic architectures from Affine Recurrence Equations and for interfacing with existing VLSI layout tools; (b) the synthesis of systolic arrays that allows the design of complicated systolic arrays consisting of a number of sub- arrays in cascade. New systolic architectures can be designed using the theory developed. The system designed also serves as a testbed for the new theory. Systolic arrays are an important class of parallel architectures that have shown great promise for exploiting the advances in VLSI technology. Since they are problem specific, the development of automated tools for synthesizing them from high-level specifications is very important. This research is directed towards Affine Recurrence Equations, which covers a general class of practical problems. The principal investigator is a new Ph.D. who already has significant progress in his research. The research focuses on important and timely topics. Support is highly recommended.
