This project focuses on the problem of power dissipation, primarily on the fundamental issues of what are the real sources of power dissipation in CMOS microprocessors, and what can be done to minimize it at a more global level. The goal is development and demonstration of techniques that would support Power-efficient Instruction Set Architectures (PISA). For this, there are four major tasks: 1. Developing technology independ models and metrics for power dissipation in CMOS logic. 2. Analyzing current day designs to benchmark the stat of the art and to indentify processor subsystems that are potential power hogs. 3. Development of new techniques that will reduce these metrics. 4. Demonstration of these techniques in a prototype CMOS PISA CPU chip. These new techniqujes will indlude gate disign level approaches, but will focus primarily on organizaitonal and instruction set architectural appropaches that inherently have a lower power requirement. The end goal of this research is to develop a deeper scientific understanding of the relationship between power and computation, and develop techniques that minimize the ratio of the two in ways that can broadly impact the continuing evolution of VLSI technology and its successful use in computing.
