The trend in electronic design is toward smaller, more powerful electronic systems composed of many VLSI chips, and their design requires new automation capabilities. This research is on the specific problem of modeling and synthesizing electronic system level interconnect, and developing algorithms and techniques that will be applicable to design automation of even broader systems. The approach is to develop a general, but approximate, capability for modeling inductive coupling of large scale system-level interconnect that is suitable for front-end design. For example, the representation of inductance coupling as a function of interconnect dimensions and spacing is being determined so that performance vs. cost trade-off analysis can be obtained. Measures of interconnect design goodness based on controlling the response damping, coupling noise, and delay are being explored. Moreover, a general approach, which addresses the complex problem of coupled lines, and includes a means of exploiting extraction capabilities is being pursued. The results of this work will also be considered for design automation of more general problems, such as electro-mechanical system design.
