Very Large Instruction Word (VLIW) Application Specific Instruction-Set Processor (ASIP) cores realize performance/power/energy tradeoffs that can be very attractive in the exceedingly competitive embedded multimedia and signal processing market. In particular, specialized datapaths comprising clusters of functional units with associated (local) register files can enable significant performance/power/energy gains over those based on centralized register files. However, such specialized datapaths pose significant research and practical challenges. The proposed research focuses on jointly addressing (1) the synthesis of VLIW ASIP datapaths, and (2) the development of high-quality retargetable compilers for such specialized processors. The proposed methodology includes a novel problem phasing/decomposition that first considers the joint binding of operations and data objects to the functional units and register files of the specialized datapath. Complementary aggressive optimization heuristics will be developed to perform datapath dependent code transformations, exploit problem symmetries to dramatically reduce the search space, and to effectively bind/assign and schedule operations, data objects and data transfers onto the datapath's resources. If this research is successful, it will contribute to technologies that will increasingly provide the competitive edge for the embedded systems industry.
