The proposed research addresses the problem of designing interconnect-optimized systems in deep-sub-micron technologies. All recent studies on the performance of VLSI systems in terms of timing, noise, power dissipation and related problems point to interconnect as a major factor. Thus, a central challenge in designing low-noise, low-power, high-speed reliable systems is to be able to estimate and optimize interconnect lengths, geometrical shapes, locations and thus delays, as well as minimize cross-talk by predicting and controlling mutual relations between individual wires. These problems are addressed by using (1) an innovative, interconnect-regular design representation (2) decomposition algorithms integrated with floorplanning and with simultaneous prediction, estimation and optimization of interconnect lengths, delays and cross-talk. The influence of process parameter variations is also considered.
