The objective of this research is to develop non-volatile computing devices, which allow the power source to be cut off at any time, and yet resume regular operation without loss of information when the power comes back. The approach is to replace all critical memory components with non-volatile units so that computing state is maintained over power interruptions. The advancement in new Flash memory devices makes this approach feasible by enabling low-voltage program/erase (P/E) around ±2V and a long (projected >1016) cycling endurance to be integrated into CMOS technology.

This research effort seeks to establish a new paradigm of computing where non-volatile memory units are used pervasively to enhance reliability against power source instability, energy-efficiency, and security. The non-volatile computing devices are especially useful for embedded cyber-physical systems enabling long running computations and data collection even with unreliable power sources. The technologies developed from this project can also benefit conventional architecture in its power optimization and internal security code generation. The project is a close collaboration between computer architecture and CMOS technology development groups, where all levels in the design hierarchy will be visited for system and technology evaluation.

This project integrates its research efforts with education by developing an undergraduate and Master curriculum that spans over the vertical design hierarchy in microprocessors. This vertical education will better prepare future work force in tackling tremendous design challenges spanning many layers of microprocessors. The results from this project will be made widely available to both industry and academia.

Project Report

Today's computer systems are mostly built with volatile memory components such as flip-flops, SRAM, and SDRAM that quickly lose information when the power supply is interrupted even for a short period of time. Such volatile devices present significant limitations for computations on embedded cyber-physical systems that have to rely on unreliable power sources. This project aimed to develop a non-volatile computing system where non-volatile elements based on flash (floating gate) devices to enable continuous computations across power failures, save static power consumption on an idle device, and enhance the security and reliability. To realize this vision, the project first designed and evaluated new non-volatile state elements (SRAMs and flip-flops) that tightly integrate non-volatile transistors into traditional volatile memory elements. Then, the project designed a prototype test-chip of a 16-bit non-volatile microcontroller compatible with TI MSP430 using these new memory elements, and showed that it is indeed feasible to build a computing device that can instantly checkpoint its state and continuously operate across power failures. Studying tightly integration of non-volatile memory in computing systems also led to innovations in areas beyond non-volatile microprocessors. For example, the idea of tightly integrating multiple memory types within a cell turned out to be widely applicable in may cases, and the project demonstrated that a hybrid memory structure combining SRAM and DRAM can significantly improve the area and energy efficiency of GPU registers. The study on flash memory also led to new security techniques. More specifically, the project found that noise and variations in the analog characteristics of the flash memory can be used to generate true random numbers, uniquely identify and authenticate each flash memory chip, and hide information. The project trained a number of PhD, MS, MEng, and undergraduate students. In particular, students from two traditionally distinct areas - semiconductor device and computer architecture - collaborated and learned how to work across disciplines. The outcome of the project was widely disseminated through publications and seminars, and test platforms were provided to other research groups for follow-up work.

Agency
National Science Foundation (NSF)
Institute
Division of Computer and Network Systems (CNS)
Type
Standard Grant (Standard)
Application #
0932069
Program Officer
Theodore Baker
Project Start
Project End
Budget Start
2009-09-01
Budget End
2014-08-31
Support Year
Fiscal Year
2009
Total Cost
$508,750
Indirect Cost
Name
Cornell University
Department
Type
DUNS #
City
Ithaca
State
NY
Country
United States
Zip Code
14850