Globalization and horizontal stratification of the semiconductor industry has exacerbated the threat of a compromise in the integrated circuit manufacturing supply chain. Specifically, intellectual property theft, unauthorized production, and hardware Trojan horse insertion are of significant concern. Further, the proliferation of advanced semiconductor fabrication equipment and expertise has enabled novel attacks against integrated circuits in the field. Recently, side-channel attacks that bypass the theoretical strength of cryptographic algorithms by exploiting inadvertent information leakage have shown to be particularly effective while requiring only a modest budget and expertise. Most extant countermeasures retrofit security features onto existing design flows, rather than build-in security from the ground up.
This project develops a novel application-specific integrated circuit (ASIC) architecture designed from the ground up to resist hardware Trojan horse insertion and have low side-channel information leakage, while still achieving high performance, low power, compact area, and future scalability. The architecture consists of an array of logic gates implemented as read-only memory (ROM) look-up tables (LUTs) interconnected by a reconfigurable network. The ROM LUTs achieve efficient operation with low side-channel emissions and are highly scalable due to their regular structure. The reconfigurable interconnect enables design obfuscation, metering of production, and complete internal node observability and controllability in order to detect hardware Trojans. The very nature of the architecture deters Trojan insertion and enables non-destructive post-manufacturing Trojan detection. The architecture has wide applicability across a range of ICs, from microprocessors to ASICs, that require efficient designs capable of secure operation