Phase transitions result in significant changes in properties of materials and occur down to nanoscale dimensions. Ferroelectric, ferromagnetic, superconductivity, etc. are examples of phase transitions which happen reproducibly and are employed in miniaturized devices. An additional phase transition phenomenon, not as commonly employed, is that of metal-insulator transitions. Ferroelectric and metal-insulator transitions are very compatible with electronic device structures, in use and in fabrication. This work aims to employ a new invention based on phase transition phenomena to achieve 10 nanometer scale non-volatile memory capable of terascale density with nanosecond speeds and low power. The work will explore the use of this component as stand-alone memory and for reconfigurability to efficiently implement computing tasks. The structure employs phase transition phenomena in a floating gate within a single element (a cross-point transistor) to achieve hysteretic characteristics at 1 V of operation at nanosecond speeds. This claim is based on an exploratory demonstration of few 1000?s of nm by 1000?s of nm dimension. The 10 nm capability will lead to 1012 bit density on integrated chips. These memory elements are programmed through control gates and can provide pass functions. This permits a very dense programmable interconnect fabric whose simplest form is the replacement of the six transistor static random access memory programming element by a single phase transition memory element.
This effort will extend the preliminary demonstration of the single element phase transition memory to nanoscale by exploring scaling, exploring new materials as replacements, developing the understanding of the underlying phenomena, and developing models for use. Such memories, in themselves, will be a very desirable robust storage medium for highly dense integrated systems. The effort will also explore the use of this new element as a programmable interconnect element. This very exploratory direction holds the promise of replacing custom design, as currently practiced, by software programmable computing where the ability to configure and reconfigure highly dense interconnections between computational elements is utilized. This part of the effort has the potential for providing major improvements in power dissipation and in mitigation of custom and expensive design and production.
The intellectual merit of the proposal is that it will explore, develop, understand, and demonstrate a nanosecond low power terascale memory element that will be of universal use. The effort will also point to new directions in achieving reliable low cost computing by implementing fast on-chip programmability at nanoscale.
The broader impact of this effort will occur through (a) development of educational class-room material for two lectures that can be incorporated in a capstone course in nanoscale device physics, (b) the inclusion of two undergraduate students, one a student from Cornell during the school year, and the second an under-represented student from outside Cornell during summer months as part of a research experience for undergraduate. The principal investigator will also organize a day-long course on advanced memories and architectures leveraging them at a major IEEE conference in the third year of this effort.