The objective of this research is to create a new class of Si-based electroabsorption modulators (EAM) that operate at an unprecedented bandwidth of 80Gb/s. The approach is to use 3D wafer bonding technology to vertically couple light into a nanowire high-index contrast silicon waveguide. A graded base SiGe heterojunction transistor is the baseline electric structure of the modulator, while the free carrier plasma effect is used to generate optical absorption modulation. Intellectual merits: For high capacity fiber-optic systems, a Si-based, monolithically integrated fast EAM is an appealing alternative technology to commercial III-V compound semiconductor based modulators. The proposed research will explore the carrier transport phenomena and its corresponding optical attenuation effect in a SiGe heterojuction transistor, as well as various design trade-offs among modulation depth, signal dispersion, operation speed, power consumption, and local heating effects. The proposed work will design a fully integrated modulator driver circuit using unmodified, silicon fabrication processes.
Broader impacts: An 80Gbps, low-power, and small footprint Si based EAM will be a breakthrough technology in advancing the development of the next generation of broadband fiber-optic networking and lightwave circuits for high-speed computing. There is a strong, synergistic educational and mentoring component for students at all levels. Outreach efforts will broaden participation of under-represented groups and undergraduate students in research programs at both institutions. K-12 outreach activities will be in collaboration with New York New Vision program at RPI, and through the Center for Engineering Educational Outreach (CEEO) at Tufts.
In year 3, the major research efforts are to develop a working and reliable working recipe at RPI cleanroom for HBT waveguide device fabrication. The major research accomplishments in processing development are summarized below. A. E-beam lithography alignment development The fabrication of HBT electro-optic modulator structure on SiGe wafer was carried on at RPI cleanroom. The major processing steps include e-beam lithography, plasma etching, chemical mechanical polishing, copper deposition to form vias. Si dummy wafers were used to develop the processing recipe. The HBT uses wedding cake structure as shown in Fig.1 (a), thus it requires multiple e-beam lithography processes to define the collector, base and emitter contacts. It is critical to develop lithography alignment with rather good accuracy. Using vernier structures with alignment markers, an alignment accuracy of 50nm is achieved as shown in Fig. 1 (b). B. Plasma etching process development In year 3, we explored the plasma etching processing with an emphasis on etching gas mix, etching rate, and choice of etching mask. A slow etching rate, smooth etching surface and waveguide side walls are the desirable qualities. Plasma etching process is followed after e-beam lithography to define the areas for emitter, base and collector contacts. Isotropic etching is key to create smooth waveguide surface that leads to minimal waveguide propagation loss. A mixture of gas of CF4, O2 and H2 is used as the plasma gas. It is observed that O2 flow rate has more pronounced effect on the etching quality, as shown in Fig. 2 where the SEM pictures were taken for samples being plasma etched with different O2 flow rate. Higher O2 to CF4 ratio leads to slower rate of the Si passivation which gives rise to a smooth etching surface. The best result is obtained with O2 in 3 sccm flow rate, as shown in Fig. 2 (b). The SiGe wafer has rather complicated chemical composition in each layer. It is key to choose the right mask during the etching process that is compliance to all layers. The most commonly used mask PMMA does not work for this case due to its low selectivity during CF4 plasma etching. Aluminum, iron and gold masks were explored and Au mask gives the best result. A Si waveguide using gold as mask after RIE etching has shown in Fig. 3. A sharp contrast on the side walls are observed and smooth etching surface is obtained. Besides choosing the proper etching mask material, a controllable and repeatable etching process is needed in order to fabricate the HBT waveguide. Veeco 3D optical profiling system is used to measure the etching depth for small feature size devices. Fig. 4(a) is a measurement file by VEECO profiling system while Fig. 4 (b) shows the characterization result of the etching rate. A slow etching rate of 69nm/min is obtained, which is rather desirable.