Intellectual Merit: Analog-to-digital converters are a mixture of analog circuits and digital blocks. The analog portion of such analog-intensive blocks requires careful design, layout, and are often the main source of power consumption and chip area. The objective of this research is to develop such analog-intensive blocks with all digital cells and automatically generate the final chip design and layout using digital synthesis tools such as Verilog. Instead of combating the challenges brought forth by the new nanometer processes, this work seeks to analyze and take advantage of these non-ideal effects. Problems such as increased offset and reduced intrinsic gain of the minimum size transistor will be addressed, and new approaches at both system and circuit levels will be explored to overcome these issues. Different structures such as stochastic analog-to-digital converter and oversampling delta-sigma modulator will be explored. Semi-analog blocks such as inverter-based integrator that would either be synthesized via existing synthesis tool (e.g. Verilog) or newly developed automatic synthesis tools will be explored. By synthesizing semi-analog and digital blocks, the proposed research will further enable highly integrated analog-intensive blocks for the next generation nanometer processes. Proficient high level modeling of blocks via synthesis tools allows fast simulation and verification, and effortless migration to another process, alleviating the typical brute-force redesigning tasks required in traditional analog-intensive blocks. A readily available synthesized digital signal processing system is also expected to further enhance the performance of these new synthesizable analog functioning digital structures.
Broader Impacts: The design methodology that will emerge from this research merges both the analog and digital functionality in the automatic synthesis of a system from a software program to an integrated circuit realization. Such combined optimization of analog and digital signal processing, as incorporated into undergraduate and graduate education, will reshape the way students approach chip design challenges. Such foundation will provide and push students to seek solutions from a much wider perspective before making the final design decisions. This training will lead to well-rounded and innovative future engineers who are well versed in both digital and analog aspects of chip design. The research results to be disseminated in prestigious journals and conferences will expose and educate the public at large and further motivate these new concepts to be investigated by other researchers. Also, the enabling ideas explored in this proposal will directly affect most portable and stationary systems, which are important segments of the microelectronics market today. The ability to automatically synthesize data converters with all-digital blocks may allow the use of these structures in digital processors, medical and bio-medical integrated circuits, and other important systems utilizing analog-to-digital interface and digital signal processing, significantly lowering the cost of integrated circuit systems.
This research aimed to use digital gates as the basic building blocks of various analog and mixed-signal circuits, mainly analog-to-digital converters (ADCs). In this process, the manual design, layout and placement of custom analog cells were eliminated. Consequently, common Verilog and VHDL scripts are used to synthesize the whole chip, including the layout and placement. This research can be especially beneficial in scaled CMOS nodes were designing custom analog blocks can be extremely difficult due to increased complexity of Dynamic Rule Check (DRC) and Layout-Vs-Schematic (LVS). The fundamentals explored in this research paves the way for analog design automation. As a result, the chip-to-market time can be substantially reduced, increasing the efficiency of the design procedure. In this work, we explored using digital gates as the fundamental analog blocks such as Opamps, analog comparators, voltage and current generators among others. Structures such as stochastic ADCs are presented which leverage the increased mismatch of the transistors in the scaled CMOS nodes to form a Gaussian distribution for comparator offset. Other efforts have focused on using semi-analog blocks to build more complicated systems such as delta-sigma modulators, mixed-mode low dropout regulators (LDOs) and analog filters. Various prototype ICs were fabricated and measured, and results are/will published in IEEE conferences and journals.