The inherent response time of electronic devices can be improved by decreasing the active device capacitance. As devices are scaled laterally using sophisticated lithographic tools, such as e-beam lithography, the devices must also be scaled vertically to ensure proper charge control. This includes the thinning of active channel and contact regions in devices such as FET's and HEMT's. Contact regions, in particular, are difficult to scale by conventional techniques such as ion-implantation. Selective etch-back and regrowth techniques will substantially influence the development of nanometer gate length devices with reduced short channel effects. Using a chemically assisted ion-beam etching system and a regrowth chamber will allow nanometer gate length devices with reduced short channel effects to be fabricated. Vertical devices are exciting because enhanced substrate currents which cause short channel effects in lateral devices are absent. Also, the critical device dimensions are grown by epitaxial techniques and hence can be made extremely small, thereby decreasing electron transit times and enhancing device speed. These and other advanced fabrication techniques will be investigated for use in producing improved performance solid state devices for integrated circuit applications.