This Small Business Innovation Research (SBIR) Phase II project will further develop a two-terminal, electronically-programmable, nonvolatile memory array using materials commonly found in integrated circuit (IC) manufacturing. Each element is smaller than a single transistor and is formed using standard IC layers. This results in a three-dimensional (3D) integrated memory (3DIM) architecture achieved using a single substrate without need to assemble multiple die or wafers together with advanced bonding techniques. The ON/OFF conductance ratio and switching speed of these devices exceed the performance of competing technologies. Current flows through nanometer-sized regions of the device, and, as a result, the memory elements will scale to smaller dimensions without reducing the current through the device, thereby resulting in a dense memory array architecture with improved signal-to-noise ratio for each subsequent IC technology. The proposed overall program will include integrating a passivation layer, connecting each element with an isolation diode, optimizing device architecture to minimize footprint, and implementing 3DIM control and drive interface electronics. The program proposed herein addresses the topic by providing material innovations for improved performance in electronics where nano-scale semiconducting filaments are fabricated within a dielectric material for commercial data storage applications.

The broader impact/commercial potential of this project are in the areas of microelectronics chip manufacturing for wireless, mobile internet and other portable devices using nonvolatile memory. Memristive device arrays impact numerous commercial markets including flash and embedded memory, and offer orders of magnitude more density as compared to conventional memory. By implementing massively dense 3D memory array architecture on a single substrate, there is no need to fabricate multiple substrates and bond them together, thereby simplifying the fabrication process, reducing manufacturing cost and increasing yield. In addition to portable devices, the proposed device may find applications in space-based earth sciences and astronomy since it is tolerant to x-ray and heavy ion radiation. Some recent approaches to achieve 3D memory on a single substrate have not been successful due to problems with external fields causing bit errors and low signal-to-noise ratio, or because device operation is based on thermal, ionic transport, or phase-change mechanisms that are inherently slow. The proposed memory elements are controlled using electrical signals rather than thermal or chemical energy, making them highly efficient and faster than competing technologies. Memory arrays will be fabricated in a commercial foundry and scaled to smaller dimensions throughout the Phase II project.

Project Report

The work performed under this program has provided new information regarding the operation and performance of a SiO2-based resistive memory (RM) device. The RM is programed using electrical signals and requires only two terminals as compared to three terminals being required for conventional memory devices, thus providing the potential for reduced size and lower cost. The established compatibility of SiO2 materials with mainstream technology will provide significant benefits in terms of integrating the device with existing manufacturing platforms. The device also has a unipolar current-voltage (I-V) response where only a single power supply is needed to program and erase the memory, as compared to bipolar memory requiring both positive and negative power supplies. Each two-terminal RM element, regardless of memory material, must have an isolation element when placed in large arrays in order to eliminate parasitic currents from affecting device operation. The combination of RM cell and isolation element forms a bitcell. The unipolar I-V response provides the benefits of being able to use a diode as the isolation element in the bitcell since current only flows in one direction, whereas bipolar devices must use transistor isolation since current flow is in both directions. Integrating a transistor into the bitcell requires increased footprint as compared to integrating a diode. As a result, the unipolar I-V response of the SiO2-based RM enables diode isolation, reduced footprint and lower cost. The work performed has established reliable design targets for integration, developed efficient electroforming and conditioning methods, and has achieved for the first time passivated devices working in air ambient. Key operating metrics demonstrated during the program include; switching endurance up to 107 cycles, switching speed ~ 40 ns, and a resistance ratio typically ~103 that can approach 108 under certain programming conditions. Thermal stress reliability data demonstrate robust static data retention at 85C for 1000 seconds. Programmed states are nonvolatile under 1 V constant stress for several hours at 150C in 1 atm air. These developments and the compatibility of SiO2 with existing technology platforms will provide significant advantages regarding integration of the RM device with mainstream manufacturing facilities, potentially leading to very high memory densities > 1 Gb/cm2 with improved reliability and enhanced performance at lower cost.

National Science Foundation (NSF)
Division of Industrial Innovation and Partnerships (IIP)
Standard Grant (Standard)
Application #
Program Officer
Muralidharan S. Nair
Project Start
Project End
Budget Start
Budget End
Support Year
Fiscal Year
Total Cost
Indirect Cost
West Lake Hills
United States
Zip Code