The objective of this proposal is to develop a new noise-aware design methodology that can maximize the error resilience of signal processing integrated circuits. As CMOS technology approaches its end-of-roadmap physical limit, there have been increasing levels of environmental and process variations, and susceptibility to noise, which make it a challenge to maintain the historical yield and reliability. This proposal will develop methodology and approaches that tackle this grand challenge in the context of signal processing integrated circuits implementation. The intellectual merit of this proposal lies in the research theme of leveraging the unique characteristics of signal processing functions to substantially improve the tolerance to noise. There are two major parts to this project: developing noise analysis techniques for signal processing integrated circuits, and exploring design space for noise-aware VLSI signal processing. In particular, this research will develop analysis techniques that can quantitatively estimate how variations in signal processing integrated circuits may affect the signal processing performance. This research will further explore the design space for noise-aware VLSI signal processing where the objective is to minimize the noise-induced signal processing performance degradation at minimal energy consumption and/or silicon cost.
The proposed research program represents the first step towards exploring a new research area. If successful, it will have broad impact on the semiconductor industry and national economy in both the near term and long term: In the near term, it will generate considerable economic benefit by improving the noise tolerance and the effective yield of signal processing integrated circuits. From another perspective, it will enable more aggressive CMOS scaling for implementing signal processing integrated circuits, which will be greatly beneficial since the signal processing functions are typically very hardware resource demanding. In the long term, this research will shed light on signal processing system implementation using post-silicon nanotechnology, such as molecular electronics, where a significant degree of noise is presumably inevitable. The education objective of this proposal is to promote the education of VLSI signal processing, the inter-disciplinary area linking semiconductor and signal processing/communication, to a wider spectrum of students.
The goal of this project was to reduce power consumption in digital circuits and digital signal processing circuits. Reducing power consumption is important to increase battery life of portable and wireless systems. Power consumption can be reduced by reducing the supply voltage of integrated circuits. However, reduction of supply voltage (termed as voltage overscaling) leads to reduced speed of the system, and will cause errors at the typical speed unless additional correction steps are taken. The goal of this project was to understand how voltage overscaling affects errors and how these errors can be corrected. In the context of arithmetic circuit design, how different multipliers and adders behave under voltage scaling scenario was not clearly understood before. The efforts in this project illustrated that what may be true for a normal voltage scenario may not be true for a voltage overscaled scenario. For example, a carruy-look-ahead adder may be an excellent adder for a normal voltage scenario, but may have higher error than a carry-ripple adder in a voltage overscaled scenario. This is because in a carry-ripple adder critical paths may not be activated often and this may lead to fewer bit errors. A second objective of this project was to design appropriate compensation filters for finite impulse response digital filters with both narrow bands as well as wide bands. In a voltage overscaled scenario, the filter output is inaccurate. Thus, a compensation filter can correct these outputs. However, how the compensation filter is designed is important. This problem was addressed in this effort. It was shown that by using a least square design method, a compensation filter can be designed based on the original filter coefficients to reduce the bit error rate and increase the signal to noise ratio. The results seem promising; however, further work is needed to demonstrate the effectiveness of this approach for a wider class of digital filters. A third contribution of this project was robust demodulation of communications systems where the symbols are transmitted using an orthogonal frequency division multiplexing system. The goal was to demodulate transmitted symbols correctly even if they have been hit by alpha particles or lightening etc. These types of noises are referred to as impulse noises. In an impulse noise scenario, many signals are affected and accurate demodulation is impossible. An iterative technique was developed to demodulate these symbols accurately in the presence of impulse noise, when the bits affected by the impulse noise are less than 10% of all the transmitted bits. This is an interesting outcome and will have applications in wireless systems, and digital subscriber lines. Further research is needed to reduce the complexity and make these approaches even more robust and more practical.
