The semiconductor industry is confronting an acute problem in the interconnect area due to the limited current carrying capability of copper wires, which are presently used to connect billions of transistors in every integrated circuit (IC) including microprocessors that are vital for information transmission, processing and storage. As IC feature sizes continue to be scaled below 45 nanometer, copper wires exhibit significant ?size effects? resulting in a sharp rise in their resistivity, which, in turn, has adverse impact both on their performance as well as reliability---in the form of current carrying capacity. This limitation of copper interconnects has been recently highlighted by various leading semiconductor companies around the world as well as in the International Technology Roadmap for Semiconductors (ITRS), and threatens to slow down or even stall the traditional growth of the semiconductor and related industries. Hence, it is critical to identify and develop new interconnect solutions.
Carbon nanotubes, tiny nanostructures 80,000 times narrower than a human hair, are known to have amazing electrical, thermal and mechanical properties, and can potentially address the challenges faced by copper and thereby extend the lifetime of ?electrical interconnects?. Most of these outstanding properties arise from the ?low-dimensionality? of CNTs---since they are essentially 1-dimensional structures. The investigators seek to, for the first time, understand how these tiny structures can be efficiently integrated into microprocessors and other circuitry to address the dire need for faster and more reliable on-chip wiring. The CNT interconnect structures also offer exciting prospects for design of ultra high-density energy storage elements (such as capacitors and inductors), as well as various system-level architectural innovations.
This collaborative four-year project brings together a team of scientists and engineers for addressing the key scientific and engineering challenges associated with the design and fabrication of CNT interconnect structures for various circuits and systems applications. The investigators employ an interdisciplinary approach that combines innovative process technology and circuit/system architecture development supported by rigorous modeling, analysis, and metrology techniques. This presents an outstanding opportunity to truly demonstrate the prospects of CNTs in overcoming one of the major limitations of nanometer scale ICs, and is expected to have wide implications for the semiconductor industry. This research will help scaling of CMOS circuits to its ultimate limits and also open new opportunities in mixed-signal, analog and radio-frequency (RF) signal processing applications as well as in 3-dimensional integrated circuit design, thereby maintaining U.S. competitiveness in the worldwide semiconductor market. Broader impact of the research includes emerging off-chip applications of carbon nanotubes as ?solder bumps? and also as an excellent thermal interface material for heat removal from chips and printed circuit boards. The overall program also ties research to education at all levels (K-12, undergraduate, graduate, continuing-education) partly via participation in programs designed by education professionals, besides focusing on recruitment and retention of underrepresented groups in nanoscience and engineering.
