Looking forward, a fundamental challenge in computer systems is the Power Wall, where, due to imbalances in technology scaling, not all the cores that can be placed in a many-core chip can be powered on at the same time. The Power Wall is transforming all levels of the system stack, including the many-core architecture landscape -- the focus of this project.
By improving power more than an order of magnitude (and energy efficiency, several times) over conventional operation, near-threshold voltage computing (NTC) has the potential to push back the Power Wall. To unlock NTC?s energy efficiency potential, however, critical barriers to NTC -- limited degree of parallelism and higher vulnerability to parametric variation -- must be attacked. This project suggests leveraging scaling characteristics and implicit fault tolerance of emerging R(ecognition), M(ining), S(ynthesis) applications in order to overcome NTC barriers.
This project will not only address critical barriers of NTC to unlock NTC?s energy efficiency potential, but also deliver tools and models to quantify the implications of these barriers at the system level. The deliverables will help the architecture community in reasoning about and exploring how to trade-off energy efficiency for resiliency in near-future systems capable of operating at as low voltages as near-threshold.
