Graphics processing units (GPUs) have rapidly evolved to become high-performance accelerators for data-parallel computing. To fully take advantage of the computing power of GPUs, on-chip networks need to provide timely data movement to satisfy the requests of data by the processing cores. Currently, there exists a big gap between the fast-growing processing power of the GPU processing cores and the slow-increasing on-chip network bandwidth. Because of this, GPU-accelerated systems are interconnect-dominated and the on-chip network becomes their performance bottleneck. The emergence of data-intensive applications, such as artificial intelligence, graph analysis, and big data is putting more pressure on the interconnection fabrics. Furthermore, the future of computing beyond Moore’s law and Dennard scaling is moving toward advanced integration of emerging hardware architectures, such as Tensor cores and high bandwidth memories through 2.5D or 3D stacking. Such new hardware architectures also call for effective support from the on-chip networks. The educational contributions of this research include: (1) develop effective strategies for teaching computer systems, create an active learning environment for students and integrate the proposed research results into the curriculum development; (2) integrate the modules and simulators into course projects and mentor students to conduct computer system related research.
This research seeks to reinvent on-chip networks for GPU-accelerated systems to remove the communication bottleneck. A major outcome of the project is a set of techniques that enable the development of effective and efficient network-on-chip architectures. The research activities leverage a combination of system modeling, state-of-the-art design methods, and cutting-edge VLSI technologies. The specific research objectives are: (1) develop computational models, benchmarks, and simulator for GPU on-chip networks, with the goal of understanding the communication behavior of GPU applications, especially the recently emerged ones; (2) develop innovative network architectures tailored for GPU-accelerated systems for improved performance and power efficiency; (3) explore the emerging research paradigm of in-network computing to improve the computation/communication efficiency.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
