This research is an investigation of techniques for efficient and effective testing of large sequential VLSI circuits. Two avenues are being pursued. First is the development of self-initializing memory elements and test time reduction techniques for circuits employing scan design. Second is development of new functional test techniques for large sequential circuits. The approach is to model large circuits as a network of finite state machines. From this model, algorithms for test generation are being developed. The algorithms are being optimized to provide good coverage for defects not modeled by stuck-at faults. Software instantiations of the test algorithms are being built.
