The objective of this research is to develop innovative radio receiver architectures and circuits with a goal to significantly improve the trade-off between power-efficiency and interference-handling capability in radio front-ends. The approach is based on low-power front-end architectures such as recursive receivers and techniques for adaptive interference cancellation and linearization. A key focus of the research will be on receivers for wireless systems with multi-mode and multi-band functionality.
Intellectual Merit: The research will include a detailed investigation of approaches to significantly alleviate the dynamic range constraint in the analog front-ends of wireless receivers implemented in short-channel complementary metal-oxide-semiconductor (CMOS) processes. Through the use of techniques such as feedforward linearization and interference cancellation, these constraints will be addressed prior to signal digitization in the receiver, while minimizing the use of external passive filters, in order to help facilitate integration of wireless transceivers in future generations of CMOS processes. A receiver architecture based on these approaches will be implemented in a 130nm or similar short-channel CMOS process.
Broader Impacts: The agile radio front-end architectures developed as part of this research are expected to impact several current and future wireless systems for diverse end-applications such as biomedical, communications and computing. The research and training program will involve student researchers at the graduate and undergraduate levels, and include students from underrepresented groups. Research results will be used to update courses, and will be disseminated through publications, seminars and websites.
