The broader impact/commercial potential of this Partnerships for Innovation - Technology Translation (PFI-TT) project is to harness “Unary computing†to significantly improve the performance of select modern applications. Cloud-based machine learning, high-frequency trading, and video / audio / signal processing used in security cameras, unmanned aerial vehicles (UAVs), and video streaming are examples of such applications. The proposed methodology improves application speed while lowering hardware cost (chip size) and power for moderate resolution computations (8-12 binary digits). Cooling costs are also reduced as a direct result of reducing the power consumption of the circuits. Speed and cost are important computer processing metrics that have real impacts on industry costs. Many modern computer applications can readily benefit from these improvements using a “plug-and-play†scheme in which traditional implementations of functions are replaced with their unary counterparts without changing the rest of the system. Cloud-based machine learning, high-frequency trading, and video / audio / signal processing used in security cameras, unmanned aerial vehicles (UAVs), and video streaming are examples of such applications.
The proposed project develops design methodologies harnessing unary computing, which is a new, unconventional paradigm in digital computing. An “uncompressed†data representation (unary) is used instead of the traditional binary representation of numbers to make computations very efficient. Limited hardware resources can perform complex calculations. Conventional methods of computer code often require many multiplications and addition operations to calculate functions such as cosh(x), tanh(x) and y=x0.45 through polynomial expansions. Unary computing is able to perform these calculations cheaply and directly without costly multiplications. These functions are widely used in applications in signal processing (image / video / audio / radar). Furthermore, unary computing can be used in significantly reducing the computation complexity of constant coefficient multiplication, which is widely used in machine learning (ML) applications. As validated by experiments, reducing computation complexity increases computation speed, reduces hardware area (size and cost of the chips to perform computations), and reduces power. The goal of this project is to develop a design toolset for automatically generating circuits for unary computing. Furthermore, a library of highly optimized hardware intellectual property (IP) blocks will be developed. The objectives of this research include developing the necessary toolset and design flows to help designers integrate the proposed technology in their electronic designs.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
