In this project, a new nanoscale three-dimensional (3-D) integrated circuit technology that can potentially revolutionize the microelectronics industry with far-reaching socio-economic impact is being investigated. The current two-dimensional (2-D) Complementary Metal Oxide Semiconductor (CMOS) technology is the main workhorse for building integrated circuits for computers, mobile devices, medical and space applications, industrial applications, and other embedded devices. While this CMOS technology, that was invented in the last century and ever since remained a key driver of global socio-economic progress, is soon expected to reach fundamental physical limits and will not be able to provide the improvements we are accustomed to. This project provides a new direction for continuous miniaturization of integrated circuits enabling continuous scaling with orders of magnitude efficiency benefits including reduced cost, as well as, a reduction of the amount of power consumption required to sustain applications at high performance. These improvements are game changing and are expected to fuel innovation in many new application domains. Another key aspect is the educational and outreach component, benefiting students and the broader technical community. This includes entrepreneurship mentoring, supporting undergraduate students for training in advanced cross-disciplinary nanotechnology concepts, international collaborations, and broad research dissemination through online technologies.
While continuous scaling of the CMOS integrated circuit architecture has been the major driver for the integrated circuits industry, scaling to sub-20nm technologies is proving to be very difficult due to fundamental physical limits. As the benefits are slowing, migrating to true 3-D eludes CMOS: its core requirements of customization and manufacturing are not inherently compatible with fine-grain 3-D integration. This project proposes a comprehensive 3-D integrated circuit fabric technology in which core fabric aspects are developed in unison to achieve 3-D compatibility. Fabric nanostructures with vertical nanowires and architected solutions for connectivity and 3-D heat management, in conjunction with a cross-layer approach across device, circuit and manufacturability, are essential to this approach. Preliminary evaluations for this 3-D nanofabric, including a designed 4-bit microprocessor, show more than 60x improvement in density with greater than 16.5x improvement in performance/watt and a potential for two orders of magnitude for very large-scale designs. Analytical projections promise further improvements over scaled CMOS. The research will focus on detailed design of core fabric aspects at nanoscale including material choices and design rules, comprehensive evaluation using a bottom-up methodology including material considerations, and nanocircuit/architecture-level designs and simulations. Experimental research will focus on validation of core fabric aspects. E-beam lithography will be used along with standard semiconductor manufacturing processes for experimental cleanroom demonstrations.
