As the interconnect characteristics dominate in deep-sub-micron regime, we are developing an interconnect-centric high-level synthesis (HLS) framework in which delay, power, and routability, can be optimized. We are investigating two approaches: (1) Incremental approach: HLS is performed iteratively by taking into account net-level estimates obtained from a detailed floorplan and global route information; and (2) Composite Approach: HLS tasks (scheduling, allocation, and binding) as well as physical design tasks (placement and routing) are unified into one composite step. The novel features of the HLS framework are: (1) use of detailed interconnect timing models (moment-based, Elmore-delay based) in HLS flow; (2) routability driven HLS; and (3) usage of Rent's exponent as a routability metric. As part of education plan, we are: (1) developing a two course sequence (dual-level); (2) experimenting in VLSI education with the case-based (Harvard Business school) teaching style (popularly used the MBA field); (3) involving undergraduate minority students in VLSI EDA research; and (4) exposing K11-12 students to the field of VLSI chip design automation.
