This research addresses design technologies for Systems on Chips and proposes a paradigm shift in their design, by focusing on a communication-centric approach that accepts and tolerates electrical-level errors within on-chip communication. The challenges of providing a fast, reliable and energy-efficient communication means on chip are addressed by designing SoCs as micro-networks of components and exploiting network technology to satisfy quality of service requirements (e.g., reliability, performance and energy bounds) under the limitation of unreliable signal transmission and non-negligible communication delays on wires.
In particular, this research addresses the design of tools to support synthesis of control protocols for micro-networks, with particular emphasis on encoding (for error detection and correction), data packetization, switching and routing issues. The merits of the proposed research relate to demonstrating how networking techniques can solve on-chip communication problems, in view of the use of advanced fabrication technologies with large spread of physical parameters, unpredictable physical layouts and on-chip information traffic.
