Over the last twenty years digital system design has gone from LSI circuits of about 10,000 gates to current designs with 10-20M gates. During this time the basic design abstraction has gone from graph based to language based using RT-level specifications. Despite numerous attempts, high level representations have not provided a practical mechanism for system level design abstraction. In this work, we are side stepping conventional behavioral approaches and are creating a new synthesis abstraction at the transaction architectural level. Fundamentally, transactions have constrained sequential and functional behavior but allow alternative construction and communication freedom. Using techniques developed for formal verification as a basis, the proposed framework promises to link architectural level modeling with sequentially constrained RT-level design. Thus, difficult trade-offs at the system level which require detailed sequential modeling can be represented within an optimization framework. The project will construct prototype tools producing RT-level output suitable for conventional synthesis as both driver and evaluation of the techniques.
