This research addresses the critical problems of design complexity, power consumption, and reliable, efficient signaling that now impede progress in digital integrated systems. Continuing progress in digital integration and performance is vital to the continued development of information technology (IT). As the number of transistors on an integrated circuit reaches the 1 billion mark, both the current monolithic design style and the globally synchronous clocking and signaling paradigm will fail. The exponential growth in complexity is causing explosions in both design time and cost. In order to achieve the social and economic IT goals of the NSF, dramatic improvements must be made in the processing power, integration, and energy efficiency of digital integrated circuits. Although transistor feature size is expected to continue to scale for at least the next fifteen years, power consumption, global signaling, and clocking have become critical problems that now prevent improvements in system performance, efficiency, and integration. The globally asynchronous locally synchronous (GALS) scheme within a network-on-chip paradigm is a good long-term solution, but this communications-centric methodology can only succeed with a fundamentally new approach to on-chip communication. The investigators are exploring new schemes for global and local communication that take advantage of the capabilities of nanometer CMOS. The communications-centric network-on-chip approach places a far greater burden on on-chip communication. Robust communication between asynchronous network components is difficult using present techniques. Modern techniques will also be stretched to their limits to provide adequate local communication. The investigators are developing a new framework for communication across a modular IC, at both the global (full chip) and local (intra-module) levels. Global communication between asynchronous modules is achieved with robust and power efficient serial links instead of traditional parallel buses. This research also concerns new circuit and interconnect structures for local (intra-module) communications and clocking. At a lower level, wires themselves are studied and optimized for both local and global signaling.
