As VLSI technology advances into ever shrinking design regimes and growing complexity, it is increasingly difficult to maintain adequate verification, process windows, and manufacturing yields. This project will investigate several newly critical issues at the interface between layout design and manufacturability, including automatic layout flows for phase-shifting masks, area fill synthesis for yield improvement, gate-length biasing for leakage variability control, and principled methodologies for exploring restricted design rules. The Intellectual merit of our proposed research stems from its broad conceptualization of a future integrated design-to-manufacturing flow, coupled with its selective focus on several key design technology goals. This work will help alleviate some of the challenges that now threaten Moore's Law and the Semiconductor Technology Roadmap.
