The server speed should always be an order of magnitude higher than the desktop speed. Growing use of gigabit ethernet on desktops and laptops requires availability of 10-gigabit over copper in data centers. These must exploit use of existing or new copper cables, and must be cheaper than their fiber based competitors. This project will address architectural design aspects and VLSI implementation aspects of the digital signal processing components of a 10-gigabit per second ethernet transceiver over copper. The challenges in design of these systems are many. At the system level, to achieve the required speed, what should be the baud rate and modulation scheme? Should one use precoding at the transmitter or equalization at the receiver? Should one use low-density parity check codes? How can one implement a 7000-tap based receiver, necessary for cancelling near end cross talk and echo for the cables, with lower power consumption? What receiver architectures are more suitable for meeting the speed requirements? What are the best solutions for implementing low-density parity check codes at 10 gigabits per second? Answers to these questions will be sought. Novel modulation schemes will be studied by hardware codesign techniques and the best architecture of a system with least area and power consumption will be sought. Availability of 10-gigabit per second data at data centers and desktops will significantly reduce the cost of deployment and increase the speed of internet access.
