Effective use of future chip-multiprocessing and multi-threaded machines will increasingly rely on the availability of parallel software. However, creating such software is sill notoriously difficult and error prone. This project explores ways of designing future parallel machines that will be easier to program in order to decrease software developmental costs, increase software reliability, and facilitate wider adoption.
Current CMP and MT architectures provide programers with only rudimentary mechanisms to control the non-deterministic ordering of events in parallel execution. This project is an integrated exploration of computer architecture and system software that will develop architectural support to explicitly track and manipulate event ordering in parallel execution. The mechanisms will allow programmers to directly express ordering constraints which are then enforced by the system, help find and debug event-ordering problems, and leverage architecture-level knowledge of intended ordering for prformance and power optimizations. Insights and results from this project wilol also stimulate further related research in computer architecture, software engineering, and programming languages.
