Application-specific instruction set processors (ASIPs) promise to offer a good tradeoff between flexibility and performance, and have been adopted widely. However, most of the research work has focused on improving performance specifically, taking a flawed assumption that low execution time always leads to energy savings. Energy-optimized ASIP synthesis and associated problems have escaped thorough scrutiny. The objective of the proposed work is to develop a new framework for energy-efficient ASIP synthesis, where a fast and accurate energy evaluation tool will be exploited to aid design space exploration, various energy optimization techniques at different levels will be applied throughout the design flow, and multiple facets of system design will be re-examined from the energy perspective. First, a hybrid energy estimation model for configurable and extensible processors in the early design cycle will be designed. The energy macro-model will capture not only the extensibility provided by additional custom hardware components through a structural macro-model, but also the configurability of the baseline processor through an instruction-level macro-model, including register file size, and pipeline issue width, etc. A set of energy-optimization techniques will be utilized during ASIP design flow systematically. Focus will be on multi-level application-specific optimization techniques, ranging from data-level storage size adaptation, to task-level parallelism extraction, up to system-level spurious switching activity suppression. Multiple facets of the system design to achieve best energy efficiency will be investigated. The proposed work will be a general study of several core technologies to enable the design, spanning the fields of compilation techniques, design space exploration, customized processor architecture generation, and high-level synthesis methodologies and tools. The ultimate goal is to expand the paradigm of ASIP synthesis along an important but not well-investigated dimension of energy efficiency. The framework and tools developed will provide an ideal mechanism through which students can interact with tangible examples of computer architecture, design hierarchy, hardware-software co-design, compiler concepts - it will allow them to rapidly prototype systems, experiment with new ideas, and thereby build intuition about embedded processor and application design.
