Commercial developments in CMOS technology make it likely that we will have 50 million-gate ASICs by 2010. Such large ASICs will be commonplace only if the EDA tools can keep up with the growing size and complexity of designs. Though this problem is widely recognized, most commercial research and development efforts have focused on semiconductor process related issues and low-level design tools as opposed to high-level design tools. The proposed research will develop a high-level design methodology and accompanying tools to enable complex digital systems to be translated into high quality physical implementations with reduced design effort. The central themes of any such methodology must be correctness by construction and rapid and transparent performance tuning. The researchers will build upon the work at MIT and elsewhere on synthesis from high-level hardware descriptions expressed as guarded atomic actions. This prior work forms the basis of the Bluespec hardware description language which has been developed by Bluespec Inc. as an extension to SystemVerilog for hardware modeling, synthesis, and verification. The researchers will use Bluespec tools as infrastructure for developing new design methodologies, synthesis algorithms, and tools. The research will focus in two specific areas. Performance specifications and associated synthesis algorithms: Currently the Bluespec compiler deduces a good schedule that satisfies the scheduling constraints detected among the guarded atomic actions. Although the automatically generated control logic enables a functionally correct by construction methodology, achieving adequate performance can sometimes be challenging. This project will develop methods to allow designers to directly specify the concurrency properties of rules and module interfaces and have the compiler generate an implementation that preserves the desired concurrency without violating correctness. Unit Transaction Level (UTL) discipline: Given a design with a deeply nested module hierarchy, the Bluespec compiler can generate arbitrarily complex control structures and long wires. The project will develop the Unit Transaction Level (UTL) discipline to be imposed on top of guarded atomic actions so that very large designs can be implemented effciently in hardware. The UTL discipline relies on latency-insensitive interfaces to allow additional registers to be inserted post-synthesis to aid in timing closure and power reduction. The UTL discipline enables designers to more clearly see how high-level design decisions will impact various physical design issues.
