CMOS VLSI Design of Low-Power Scalable Heterogeneous Networks for Multi-Core Systems-on-Chip.
During the past decade, interconnects have replaced transistors as the dominant determiner of integrated circuit performance by imposing primary limits on latency, energy dissipation, signal integrity and design productivity for giga-scale integration. Low-latency, low-energy circuits for communications will require regular, structured interconnect to engineer wires and tune circuits to those wires. On-chip networks (OCN) provide such a structured fabric in which communication is obtained by routing packets through a general-purpose interconnect structure rather than using a design-specific ad hoc global wiring network routed by CAD tools. The PIs will investigate the design of scalable OCNs for multi-core systems-on-chip by combining a new low-latency, low-energy, current-mode signalling approach based on damping compensation with the design of latency-insensitive communication protocols extended to support fault-tolerant communication as well as dynamic voltage and frequency scaling and power-down for the cores.
The beginning of the new century has seen a major paradigm shift in the design of complex integrated circuits such as the microprocessors that empower a variety of computing systems from data centers to desktop/laptop computers and embedded devices such as smart phones. Due to a combination of multiple factors including the increasing impact of on-chip power dissipation and intra-chip global interconnect delay and the need of managing the design complexity of realizing chips that host tens of billions of transistors, most digital integrated circuits are now designed through the assembly of a growing number of heterogeneous processing elements. This shift from traditional architectures with a single processing core to the new generations of so-called multi-core systems-on-chip with tens of processing cores requires the realization of a distributed computing system on a single piece of silicon of a few tens millimeter square. In any distributed system communication plays a central roe and, indeed, the design of on-chip interconnect infrastructure has become the dominant determiner for the performance of multi-core systems-on-chip. Specifically, the design of on-chip interconnects impact the exchange of data among the processing cores, the overall energy necessary to perform a computation as well as, at design time, the productivity of the team of engineers working on the realization of the overall system-on-chip. The introduction of ideas borrowed from the filed of computer networks can help engineers to optimize the design of on-chip interconnects along all the above axis because high-performance, energy-efficient, modular, and scalable communication infrastructures can be better obtained through the use of regular and structured interconnect. As part of this NSF project, the PIs have conceived, designed, optimized, and fabricated a network-on-chip (NoC) for the next generation of multi-core systems-on-chip. The NoC is based on an innovative heterogeneous architecture that combines two different networks: a packet-switched network and a circuit-switched network. The packet-switched network uses traditional signaling modes and is used to transmit low-priority messages and perform small data transfers among the processing cores. The circuit-switched network, instead, offers a low-latency, high-bandwidth, energy-efficient solution for the exchange of high-priority data transfers and large messages among processing cores that may seat at opposite ends of the chip. The main research outcome of this project has been the fabrication of a prototype integrated circuit of approximately eighty square millimeters in a 90nm CMOS process hosting an instance of the proposed NoC architecture that connects sixteen simple programmable cores. Additional research findings include the development of new protocols for both link level and end-to-end flow control of NoCs, as well as the design and validation of a new class of interface circuits that support more efficient system-level design-exploration methods for complex multi-core systems-on-chip. In terms of broader impact, the PIs have performed various activities spanning professional service, education program development and outreach. For instance, the PIs have taken multiple leadership roles in conference organization, such as serving in various capacities (local arrangement chair, publication chair, and technical program committee co-chair) across subsequent editions of the recently-established International Conference on Networks-on-Chip. This project was also accompanied by a strong effort in high-school outreach activities, through the establishment of a new educational program at Gompers Career and Technical Education High School, a New York City public high school located in the Bronx. As part of this successful initiative, which takes place once a week for a period of twelve weeks in each semester term, Columbia graduate students have worked closely as tutors for the senior-level pre-engineering class of high-school students. Each semester is subdivided into three project-based engineering design modules and each module is taught by a different pair of graduate students who brings their own creativity and interests to the classroom. Each of these projects builds on coursework that the students have taken throughout high school and encourages them to apply their knowledge to practical engineering design.
