Current technology trends predict continued transistor shrinking but less improvement in switching speeds and energy efficiency. These trends have led industrial and academic computer architects to abandon their traditional staples of single-thread performance and high-clock rate designs and to rally around multi-core designs as the best hope for continued exponential improvements in performance and power efficiency. Traditional multi-core designs are effective at providing throughput for workloads with abundant explicit thread-level parallelism, but the vast majority of current programs have few or no explicit programmer-visible threads and thus do not observe substantial benefits.
This proposal describes ON-Core (short for Operand Network Core and pronounced "encore"), a new multi-core design that provides increased single-thread performance by the transparent aggregation of multiple cores. Inspired by both the pioneering speculative multithreading work and recent advances in the scaling of traditional single-core designs, ON-Core abandons the philosophy of adding only minimal speculative multithreading hardware support to an existing multi-core design. Instead, ON-Core uses a new microarchitecture that is specifically designed to support segmentation/aggregation. An ON-Core chip can flexibly act as either a traditional multi-core for high multithreaded throughput or as a tightly integrated speculatively multithreaded multi-core that provides high single-thread performance without compiler support.
