Multicore and multithreaded processors are replacing single-threaded processors in high-performance computer clusters, servers, workstations and high-end personal computers. The memory demand of those processors increases proportionally with the degree of multithreading. The proposed research aims to alleviate the memory bandwidth pressure by using new methods of memory access scheduling and by adjusting multithreaded execution in accordance with memory bandwidth pressure. A set of interdependent and complementary approaches are proposed: Urgency and confidence levels of memory accesses are used to guide the memory access scheduling; memory load index is used to control the progress of multithreaded execution; memory accesses from multiple threads are smoothed out to avoid bandwidth congestion; and several prediction-based techniques are proposed to reduce cache miss penalty in deep cache hierarchies. All together, both the processor computing power and the memory bandwidth will be better utilized; and higher system throughput can be achieved. The proposed research will help high-performance computing applications benefit from the emergence of highly multithreaded processors by alleviating the crucial bottleneck of off-chip memory bandwidth. It will also deepen the understanding of complex interactions between highly multithreaded processors and their memory subsystems, which will complement education in computer architecture and parallel computing.
