It is expected that CMOS, today's technology of choice for semiconductor-based integrated circuits, will soon run into fundamental physical limits mainly due to the lithographic process used to pattern the circuits. Among all possible successors, non-lithographic molecular-electronic technology based on carbon nanotubes and nanowires is one of the most promising. Because of inherent fabrication difficulties, circuits in those technologies will exhibit large variations in physical parameters as well as large percentage of faults and defects. Taking parameter variability and defect- and fault-tolerance into account will be an inherent part of any successful circuit design methodology in the nanoscale era.
Because any variation in an electrical parameter has an effect on the timing behavior of the circuit, being able to design a circuit in a manner such that the correct behavior of the circuit is independent of the timing is a great advantage since it would greatly increase the robustness of the circuit to parameter variations. Such a design style is called ``asynchronous''. The purpose of this research is to develop a design method for molecular-electronic integrated circuits based on asynchronous logic, including error- and defect-tolerance circuit techniques. Another reason for using asynchronous logic is that such logic does not need a clock to implement the sequencing of actions in a typical digital system like a microprocessor. Distributing a clock signal across a chip requires long wires with well-balanced timing properties, which is impossible to do in molecular electronic.
The research will develop design methods to deal with both hard defects like broken wires, and soft (or transient) errors as caused for instance by an alpha particle hitting the circuit and changing a bit from zero to one. Dealing with hard errors will require redundancy to be able to use ``spares'' and reconfigurability to redesign a circuit on the fly to circumvent an error. For all those unpredictable changes in the circuit, independence of timing offered by asynchrony will be a great advantage.
Because of the non-lithographic nature of the fabrication process, molecular electronics restricts the geometry of the chips. Essentially, a wire can run either north-south or east-west, and all active devices (transistors) are built at the intersection between a north-south wire and an east-west one. This restricted geometry calls for large regular structures like FPGAs, rather than random logic with arbitrary geometry. Designing within this restricted geometry (with the additional issue of very highly resistive contacts between wires of different direction) is another challenge of this project.
The project will propose and test a complete asynchronous logic family for molecular electronic devices based on carbone nanotubes and nanowires and a design method to deal with different aspects of fault- and defect-tolerance. It is hoped that a significant chip, for instance a small microcontroller, will be designed and fabricated.
