The 3D integrated circuit is an emergent technology that vertically stacks multiple die with a die-to-die interconnect. The die-to-die via pitch is very small and provides the possibility of arranging digital functional blocks across multiple die at a very fine level of granularity. This results in a decrease in the overall wire length, which translates into less wire delay and less power. Advances in 3D integration and packaging are undoubtedly gaining momentum and have become of critical interest to the semiconductor community. These 3D integrated circuit and package manufacturing technologies are rapidly being adopted by several leading companies for commercial applications. In spite of the rapid advancement in 3D fabrication and packaging technologies, the design automation community has seen very little progress on the development of computer-aided design tools for 3D integration. The goal of this research is to develop physical design algorithms for 3D integrated circuits. We perform placement and routing at two levels of design abstraction: microarchitecture and circuit level. Our objective is to optimize performance, power, and size while addressing several important reliability issues such as thermal hot-spot, leakage power, and power-supply noise.
The intellectual merit of the research is to conduct the first detailed hierarchical study on how 3D technology impacts the organization of processor microarchitectures and their circuit implementation. First, 3D-aware design decisions as early as in the microarchitectural floorplanning stage are crucial in addressing the opportunities and challenges for using 3D technology. Second, a proper management of the thermal-via, through-the-silicon-via, and decoupling capacitor is a highly effective means of alleviating the ever-worsening thermal, leakage, and power-supply noise problems in 3D integrated circuits. Third, retiming is a powerful tool to reduce both dynamic and leakage power under performance constraints while considering the statistical behavior of the gate and interconnect delay caused by process variations. Finally, we are investigating a number of interesting topology styles for the 3D clock network and demonstrate how to consider clock skew variation under thermal and voltage variations. The broader impact of the research is to call for a very strong collaboration between researchers from the microarchitecture and EDA/physical design areas that will bridge the disciplines to deliver better processor technologies. Similarly, students working on the research are gaining multi-disciplinary and cross-cutting experience from low-level areas such as circuit design, physical design, thermal modeling, and noise modeling, to high-level topics, including microarchitecture design and multi-objective/multi-constraint optimization algorithms.
The 3D integrated circuit is an emergent technology that vertically stacks multiple die with a die-to-die interconnect. The die-to-die via pitch is very small and provides the possibility of arranging digital functional blocks across multiple die at a very fine level of granularity. This results in a decrease in the overall wire length, which translates into less wire delay and less power. Advances in 3D integration and packaging are undoubtedly gaining momentum and have become of critical interest to the semiconductor community. These 3D integrated circuit and package manufacturing technologies are rapidly being adopted by several leading companies for commercial applications. In spite of the rapid advancement in 3D fabrication and packaging technologies, the design automation community has seen very little progress on the development of computer-aided design tools for 3D integration. The goal of this research is to develop models, design techniques, and physical design algorithms for 3D integrated circuits. We perform modeling for various reliability issues and develop placement and routing at two levels of design abstraction: microarchitecture and circuit level. Our objective is to optimize performance, power, and size while addressing several important reliability issues such as thermal hot-spot, leakage power, and power-supply noise. We summarize our findings and accomplishments as follows: (1) We found that the existing algorithms for the conventional 2D ICs cannot be extended in a straightforward way to handle 3D ICs. We also learned that 3D algorithms that were developed from the scratch instead of extending 2D algorithms were more effective. (2) We learned that the thermal issues were indeed serious in 3D stacked ICs and that there is a significant room for improvement at the physical design stage. We have developed thermal-ware algorithms for various stages of physical design such as floorplanning, signal routing, and clock routing. (3) We learned that the existing 3D wirelength distribution models overlooked the importance of the area impact of TSV (through silicon via). We learned that the impact of TSV, in fact, is not just on the layout are, but it also affects wirelength, performance, and reliability. We proposed a more accurate 3D wirelength distribution model and validated our claims. (4) We learned that power delivery will most likely to ultimately stop stacking more dies in 3D stack. In our 'many-tier' 3D stacking limit study, we use a prototype 3D system that contains 46 tiers and built a power delivery network. Even with aggressive optimization, we showed that power delivery will eventually become a limiting factor. (5) We learned that being able to test individual dies before stacking is very important to improve the overall yield of 3D ICs. One of the essential element in this so called 'pre-bond' testing is a 3D clock tree that provides clock signal to individual dies during testing and to all dies during normal operation. In this case, we showed how to use multiple TSVs to reduce the overall wirelength while providing pre-bond testabilty and post-bond operability. (6) We learned at various TSVs become routing obstacles during clock tree synthesis. We found ways to avoid them while maintaining minimum skew and power. (7) Block-level 3D ICs involve design effort at the floorplanning stage. We developed a 3D floorplanning engine that considers the area overhead of TSVs. (8) We developed algorithms to compute delay of 3D interconnects that contain TSVS and add buffers to reduce the delay. (9) We investigated the current crowing phenomena in P/G TSVs and developed models to be used in full-chip IR-drop analysis. (10) We studied die-to-die thermal coupling in 3D ICs and developed gate-level placement tool to alleviate hotspot issues. (11) 6. we investigated the impact of packaging elements to the mechanical reliability of the entire chip-package 3D IC system and developed ways to obtain stress map. (12) 7. We developed algorithms to build clock trees that utilize array-style clock TSVs for low power applications. The intellectual merit of the research is the several pioneering research tasks we performed on modeling, design, and CAD tools for 3D ICs mentioned above. The broader impact of the research is the collaboration between researchers from the microarchitecture and EDA/physical design areas that bridged the disciplines to deliver better processor technologies. Similarly, students working on the research gained multi-disciplinary and cross-cutting experience from low-level areas such as circuit design, physical design, thermal modeling, and noise modeling, to high-level topics, including microarchitecture design and multi-objective/multi-constraint optimization algorithms.
