Over the years, the underlying design philosophy of electronic design and analysis tools has undergone paradigm shifts from area optimization to timing optimization to power optimization and now is shifting to reliability-centric design optimization. Understanding of the interplay between errors, power dissipation in a chip with its associated side effects, and reliability problems will be the key to commercial success of sub-30nm silicon and nonsilicon technologies. It is expected that statistical theories and probabilistic methods will play significant role in the design of such reliability-centric CAD tools. In this context, the career research goal of the PI is to construct reliability-centric design and analysis tools for the inter-coupled issues of error, power and redundancy for nano-CMOS and other emerging nano-devices, such as quantum-dot cellular automata. There are two main thrusts : one in medium term problems and the other in long term problems. First, in the medium term category are problems related to nano-CMOS for which the PI will research reliability-centric design optimization and analysis tools at logic level for error, power, and reliability of nano-CMOS, taking into account process variability and circuit topology. These models would allow probabilistic abstraction of technology-dependent parameters, such as device characteristics, process parameter variations, and thermal issues, in addition to, structural dependencies among the interconnected components and input uncertainties. In the long term category are problems in novel computing paradigms using emerging nano-devices such as field-coupled computing architectures using quantum-dot cellular automata. The basic issues considered will still be the same, i.e. error, power, and reliability; however, the modeling of these will be driven by the physics of these devices to a larger extent than nano-CMOS. The career teaching goals of the PI spans traditional pedagogic activities, such as developing new courses, and educational research related to VLSI education, such as testing the hypotheses that (a) active learning, based on sensory mode of a student, or (b) "Learning by doing" promotes deeper understanding of VLSI concepts.
Over the years, the underlying design philosophy of EDA tools has undergone paradigm shifts from area optimization to timing optimization to power optimization and now is shifting to reliability-centric design optimization. The career research goal is to construct reliability-centric design and analysis tools for the intercoupled issues of error, power and redundancy for nano-CMOS and other emerging nano-devices. It is expected that statistical theories and experimental methods will play a dominant role in the design of such reliability-centric CAD tools. The research outcomes are: We proposed a probabilistic error model based on minimal graphical probabilistic model namely Bayesian networks to estimate this expected output error probability, in the context of probabilistic computing. We also provide upper bounds of errors that are circuit-specific and can actually diagnose the worst case input vectors for which special redundancies have to be employed. We studied the interplay of computing error behavior with delay or latency of computation induced by the clocking scheme. We also offered an efficient method to compute the N lowest energy modes of a clocked QCA circuit. We modeled the QCA cell arrangement in each zone using a graph-based probabilistic model, which is then transformed into a Markov tree structure defined over subsets of QCA cells. Using this model we studied the trade-off between switching errors and clocking zones. Designed a power model for Quantum-dot cellular automata paradigm. Due to their small sizes, power is an important design parameter. In this work, we derive an upper bound for power loss that will occur with input change, even with the circuit staying at respective ground states before and after the change. This bound is computationally efficient for large QCA circuits since it just requires the knowledge of the before and after ground states due to input change. We categorize power loss in clocked QCA circuits into two types that are commonly used in circuit theory: switching power and leakage power. Our model provides an estimate of power loss in a QCA circuit for clocks with sharp transitions, which result in non-adiabatic operations and gives us the upper bound of power expended. Proposed reliability and defect characterization for Magnetic cellular automata based on fabricated nanostructures. Most important work in this domain was magnetic in-plane crossings and reliability characterization of magnetic wires. Proposed clocking schemes and magnetic layouts for single layer and multi-layer magnets that can be integrated with CMOS to access and control. We also proposed variation-aware read mechanism for the the multi-layer Magnetic tunnel junction based logic. We were the first to experimentally show Field coupled computing using Magnetic tunnel junctions. This work leads to not only a very dense memory but also a thermally robust logic as a backup computing element in memory. We have created a framework for non-Boolean computing by creating a new phase plots for coupled magnetic nanodots and experimentally observed the two ground states vortex and single domain at the same fabricated dimension which could have treendous impact on future non-Boolean frameworks. Career Education Outcomes We have proposed a knowledge module in the undergraduate logic design course introduced to electrical engineering and computer science students exposing them to nano-computing concepts. A preliminary implementation of the proposed knowledge module that exposes undergraduate students to nano-computing concepts yielded the following responses, Students showed motivation towards learning more about nanotechnology and nanocomputing in an effective and understandable way. It also strengthened their knowledge in Kmaps and helped them develop cognitive skills to apply this knowledge in a very novel way. We also proposed knowledge units on Engineering Ethics and Sustainable Designs, Carbon nanotube based circuits, majority logic synthesis and nanomagnetic/memristive logic as well as neuromorphic threshold logic in the Logic Design Course. Career Broader Impact Outcomes PI Bhanja is actively involved in educational outreach programs such as REU, RET, and REHS. And Bhanjs is particularly sensitive about the low representation of underrepresented, minority (URM) and women in engineering and STEM. Out of the six PhD students graduated from this CAREER grant, four were from minority/underrepresented group. She is also the coordinator for the SLOAN foundation scholarship program representing EE, USF and is responsible for recruitment and retention. She has organized CRAW-sponsored Distinguished Lecture Series for motivating USF students towards graduate school. She is also involved with elementary and high school students targeting Nano-computing education (http://ncrg.eng.usf.edu/outreach/outreach.htm). PI Bhanja is engaged with communities through Science symposium held in MOSI and Great-American-Teach-In in Hillsborough county and is a member of Florida Robotics Alliance Board where she participates in planning and volunteering for the first "BEST" robotics competition held for K-12 students in the Tampa Bay.
